ISE
Implementation Overview for FPGAs
After synthesis, you run design implementation, which comprises the following steps:
  1.  Translate, which merges the incoming netlists and constraints into a Xilinx® design file
  2.  Map, which fits the design into the available resources on the target device
  3.  Place and Route, which places and routes the design to the timing constraints
  4.  Programming file generation, which creates a bitstream file that can be downloaded to the device
In the Sources tab, select Implementation from the Design View drop-down list, and select the top module Image. In the Processes tab, double-click Implement Design to run the implementation process in one step, or double-click Translate, Map, and Place & Route to run each of the implementation steps separately. To generate the programming file, double-click Generate Programming File. Alternatively, you can select Process > Implement Top Module to run Implement Design on the top module. For details, see Implementing the Top Module.
Default property values can be set for the Implement Design process or for each of the separate implementation processes. Image These properties values can also be changed using the Design Goals & Strategies command, available from the Project menu. For details, see Using Design Goals & Strategies.
Note In addition to the regular implementation flow described here, alternate implementations to save runtime and preserve results can be used. For more details, see the Partitions Overview and Using SmartGuide.
Translate
The Translate process merges all of the input netlists and design constraints and outputs a Xilinx native generic database (NGD) file, which describes the logical design reduced to Xilinx primitives. See the following table for details.
 
Translate Process
Command line toolNGDBuild
Tcl commandprocess run "Translate"
Input filesEDIF, SEDIF, EDN, EDF, NGC, UCF, NCF, URF, NMC, BMM
Output filesBLD (report), NGD
Process propertiesTranslate Properties
Tools available after running processConstraints Editor, Floorplan Editor, Floorplanner, PACE Image
Note  Each of these tools modifies the UCF file. When you rerun Translate with the updated UCF, the NGD file is updated.
Map
The Map process maps the logic defined by an NGD file into FPGA elements, such as CLBs and IOBs. The output design is a native circuit description (NCD) file that physically represents the design mapped to the components in the Xilinx FPGA. See the following table for details.
 
Map Process
Command line toolsMAP
Tcl commandprocess run "Map"
Input filesNGD, NMC, NCD, NGM
Note  The NCD and NGM files are for guiding.
Output filesNCD, PCF, NGM, MRP (report), GRF, MAP, PSR
Process PropertiesMap Properties
Tools available after running processFloorplanner, FPGA Editor, Timing Analyzer Image
Place and Route
The Place and Route process takes a mapped NCD file, places and routes the design, and produces an NCD file that is used as input for bitstream generation. See the following table for details.
 
Place and Route Process
Command line toolsPAR
Tcl commandprocess run "Place & Route"
Input filesNCD, PCF
Note  In addition to the NCD file from MAP, PAR also accepts an NCD file for guiding.
Output filesNCD, PAR (report), PAD, CSV, TXT, GRF, DLY
Process PropertiesPlace & Route Properties
Tools available after running processFloorplanner, FPGA Editor, Timing Analyzer, TRACE, XPower Analyzer Image
Programming File Generation
The Generate Programming File process produces a bitstream for Xilinx device configuration. After the design is completely routed, you must configure the device so it can execute the desired function. See the following table for details.
 
Generate Programming File Process
Command line toolsBitGen
Tcl commandprocess run "Generate Programming File"
Input filesNCD, PCF, NKY
Output filesBGN, BIN, BIT, DRC, ISC, LL, MSD, MSK, NKY, ISC, RBA, RBB, RBD, RBT
Process PropertiesGeneral Options, Configuration Options, Startup Options, Readback Options, Encryption Options
Tools available after running processiMPACT Image
Additional Resources
Additional details are available in the following Xilinx® documentation:
DocumentationTopics Covered
Development System Reference GuideCommand line tools, Tcl command information
See Also

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