After configuring your device, you can debug your FPGA design using ChipScope™ Pro software.
From the Project Navigator Processes tab
, double-click Analyze Design Using
to launch the ChipScope Pro Analyzer. To use this
process, you must purchase the Xilinx® ChipScope Pro software and
must design with debug and verification in mind, as described in the
ChipScope Pro comprises the ChipScope Pro cores in the
CORE Generator, the ChipScope Pro Core Inserter, and the ChipScope Pro Analyzer.
For more information on ChipScope Pro, including how to purchase, see
the ChipScope Pro
ChipScope Pro Design Flow Overview
the ChipScope Pro software to perform in-circuit verification, you must
do the following:
- Insert ChipScope Pro cores in your design using the CORE Generator or
- Implement your design in Project Navigator and configure your device.
- Analyze your design using the ChipScope Pro Analyzer.
ChipScope Pro Core Insertion
You can insert ChipScope Pro cores
in your design with the ChipScope Pro tools using one of the following
Each flow offers its own advantages, as shown in the following
|ChipScope Pro Core Generator and HDL Instantiation Flow||ChipScope Pro Core Inserter Flow|
|- Core generation and insertion are separate steps||+ Core generation and insertion are one step|
|+ Standard implementation flow ||- Core Inserter performs part of the Translate process|
|- HDL code must be modified||+ HDL code does not require modification|
|+ Every node is available for debug||- Only post-synthesis nodes are available for debug|
|- To exclude cores, comment them out of the HDL code||+ To exclude cores, remove the CDC file in Project Navigator|
|+ VIO cores are easily inserted||- VIO cores are not available|
ChipScope Pro Cores
ChipScope Pro allows you
to embed the following cores within your design, which assist with
on-chip debugging: integrated logic analyzer (ILA), integrated bus
analyzer (IBA), and virtual input/output (VIO) low-profile software
cores. These cores allow you to view internal signals and nodes in
your FPGA, including the IBM® CoreConnect™ processor local
bus (PLB) that supports the IBM PowerPC™ 405. Following
are the ChipScope Pro cores and their functions:
The Integrated Controller (ICON) core provides the
communication between the embedded ILA, IBA, and VIO cores and the
computer running the ChipScope Pro Analyzer software.
The ILA core is a customizable logic analyzer core
that can be used to monitor the internal signals in your design. Because
the ILA core is synchronous to the design being monitored, all design
clock constraints applied to your design are also applied to the components
inside the ILA core.
The Agilent Trace Core 2 (ATC2) is a customizable
logic analyzer core, which is similar to the ILA core but does not
use on-chip Block RAM resources to store captured trace data. The
ATC2 core synchronizes ChipScope Pro to the Agilent FPGA dynamic probe
technology, delivering the first integrated application for FPGA debug
with logic analyzers.
The virtual input/output core is a customizable core
that can both monitor and drive internal FPGA signals in real time.
Unlike the ILA and IBA cores, the VIO core does not require on-chip
Note EDK provides additional specific cores. For more information,
refer to the "Configuring PLB IBA ChipScope Cores" topic in the XPS
Help System in EDK.
The ChipScope Pro Analyzer
tool interfaces directly to the ChipScope Pro cores. Use this software
to download designs, set trigger conditions, and display data. You
can show data as waveforms, lists, or graphs, and can tokenize values.
For detailed information on analyzing the cores, see the ChipScope Documentation
are available in the following Xilinx documentation: