Xilinx Teams with Leading Universities Around the World to Establish Adaptive Compute Research Clusters

World-class research clusters at top universities to spearhead novel research into all areas of adaptive compute acceleration

May 05, 2020

World-class research clusters at top universities to spearhead novel research into all areas of adaptive compute acceleration

SAN JOSE, Calif.--(BUSINESS WIRE)-- Xilinx, Inc. (NASDAQ: XLNX), the leader in adaptive and intelligent computing, today announced it is establishing Xilinx® Adaptive Compute Clusters (XACC) at four of the world’s most prestigious universities. The XACCs provide critical infrastructure and funding to support novel research in adaptive compute acceleration for high performance computing (HPC). The scope of the research is broad and encompasses systems, architecture, tools and applications.

The XACCs will be equipped with the latest Xilinx hardware and software technologies for adaptive compute acceleration. Each cluster is specially configured to enable some of the world’s foremost academic teams to conduct state-of-the-art HPC research.

The first of the XACCs is installed at ETH Zurich in Switzerland. XACCs will follow at the University of California, Los Angeles (UCLA) and the University of Illinois at Urbana Champaign (UIUC). A fourth cluster is being setup at the National University of Singapore (NUS). The XACCs are composed of high-end servers, Xilinx Alveo™ accelerator cards and high speed networking. Each Alveo card has two connections to a 100Gbps network switch to allow exploration of arbitrary network topologies for distributed computing.

The high-end servers are equipped with the latest Xilinx software including Vitis™, a unified software platform for software engineers, AI researchers and data scientists who want to exploit adaptive compute acceleration. All four XACCs are expected to be operational within the next three months. They will be expanded with the newest 7nm Versal™ Adaptive Compute Acceleration Platform (ACAP) in a future deployment.

“With the decline of Moore’s law, we are entering an exciting era where the next wave of computing systems will look very different to what we have seen in the past, and adaptive compute accelerators will play a key role,” said Ivo Bolsens, CTO and senior vice president, at Xilinx. “The XACCs will provide dedicated hubs for innovation and research collaboration that will drive the development and integration of new adaptive compute technology into next generation systems.”

Xilinx invites leading academics to join the XACC program and collaborate on state-of-the-art HPC research on clusters equipped with the latest Xilinx adaptive compute acceleration technologies. Partner research teams will be able to remotely access the clusters’ computing resources to carry out their own research in adaptive computing. The XACCs will also act as a community hub for researchers to come together to collaborate with other experts in the field, including Xilinx in-house research groups.

The cluster at ETH Zurich will be led by Prof. Gustavo Alonso, head of the Institute for Computing Platforms and a member of the Systems Group in the Department of Computer Science, and will focus on network and database acceleration.

“The clusters that Xilinx has made available to researchers offers a unique opportunity to explore the latest technology at an unprecedented scale and ease of use,” said Prof. Alonso. “The clusters will enable new research as well as help establish a much-needed infrastructure for sharing designs, results, tools, and ideas in a reproducible manner.”

The cluster at UCLA will focus on energy-efficient computing, customized computing for big-data applications and highly scalable algorithms. Prof. Jason Cong, Director for the Center for Customizable Domain-Specific Computing at UCLA Samueli School of Engineering, will lead the effort. Prof. Cong has been at the forefront of FPGA technology research for more than 30 years.

“We very much appreciate the contribution of the Xilinx Adaptive Compute Cluster,” said Prof. Cong. “It will greatly facilitate our research programs on graph-based machine learning, video analytics, genomics and precision medicine. The offering of high-bandwidth memory (HBM)-based FPGAs in this cluster is especially timely and helpful as many computation steps in those research projects are memory-bound.”

The cluster at UIUC will be based in the Illinois’ Coordinated Science Lab and will build on many years of research and education work in high performance and heterogeneous computing at UIUC. Specific topics include novel multi-FPGA topologies connected through high-speed links and switches, security and memory coherence for a network of FPGAs, efficient peer-to-peer data transfers, FPGA accelerators for processing SSD data, and compilers and system tools targeting high performance, high programmability and portability.

The center will be led by Prof. Deming Chen, Abel Bliss Professor of Engineering, and Prof. Wen-Mei Hwu, AMD Jerry Sanders Chair of Electrical and Computer Engineering (ECE), both with the ECE Department.

“The center funding together with the hardware donation will enable us to carry out new research and educational activities that were not possible before,” said Prof. Chen at UIUC. “We will build novel, experimental FPGA-centric compute systems and develop domain-specific compilers and system tools targeting high-performance computing. We will focus on several important application domains, including AI with deep learning, large-scale graph processing, and computational genomics. Several undergraduate and graduate-level courses will benefit from the research activities and access to the cluster. We also plan to engage several other universities to exchange experience, share computation resources and pursue collaborative projects.”

The cluster at NUS will boost new systems and applications research and development with heterogeneous computing platforms. It will also become a hub for attracting researchers and students from Asia to promote international collaborations as well as for establishing a global test-bed with the other XACC centers in Asia, Europe and the United States.

The research will be led by Associate Professor Bingsheng He, Associate Professor Weng-Fai Wong and Professor Tulika Mitra from the Department of Computer Science at the NUS School of Computing. Assoc. Prof. He serves as Chair of the Joint Academic Committee of Computer Engineering Program and Assistant Dean (Graduate Studies) at the School.

“We would like to acknowledge the generous support from Xilinx to set up this research infrastructure at the NUS School of Computing,” said Assoc. Prof. He. “Our colleagues have been conducting pioneering research with FPGAs in different domains, such as database, machine learning, systems and networking, internet of things, and computer architecture. With the leading-edge FPGA platforms from Xilinx, we envision that this computing cluster will play a central role in cultivating exciting new research, educational initiatives, and collaborations in NUS, Singapore, and beyond.”

Researchers who would like to participate in the XACC program are invited to contact the Xilinx University Program (XUP) to learn more and apply for access to the XACC hardware. See www.xilinx.com/university for more details.

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About Xilinx

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies – from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs, and the ACAP, designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent, and connected world of the future. For more information, visit www.xilinx.com.

© Copyright 2020 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Versal, Vitis and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

Source: Xilinx Newsroom
Category: Corporate Announcements

Brian Garabedian
Brian.garabedian@xilinx.com

Source: Xilinx, Inc.