Edgecortix Dynamic Neural Accelerator® DNA-F200

Dynamic Neural Accelerator® DNA-F200 is Edgecortix's second-generation (F-series) high-performance convolution neural network (CNN) inference IP designed for FPGAs. It is optimized for ultra-low latency, energy-efficient and high throughput workloads for streaming data. Running at 300 MHz, it provides a peak INT8 throughput of 3.7 Top/s. Complemented by Edgecortix’s proprietary MERA™ dataflow compiler, nearly zero effort will be required for deployment of deep neural networks designed in most popular frameworks like Pytorch and Tensorflow-lite directly on the Xilinx U50/U50LV FPGA boards.

Vendor: Edgecortix Inc

Last Update: February 10, 2020

Size: 1 GB

Container Version: f200_u50_v1.0

Try or Buy

Obtain an entitlement to evaluate or purchase this product.

Begin a free trial and run the application example below.

View and purchase available pricing plans for this application.

Deployment Options

This application is containerized and can be easily run in a few minutes in the cloud, or on-premises.

On Premises
Alveo U50
View & Buy Product
  • Xilinx Runtime: 2020.2
  • Target Platform: xilinx_u50_gen3x16_xdma_201920_3


Start Evaluation

Follow the instructions based on your deployment method.

Alveo U50


Obtain an Account Access Key

An access key is required to authenticate a user and grant them access to the application based on their entitlements.  To obtain your account access key, follow these steps:

  • Login to the Xilinx App Store Portal
  • Click the button labeled “Manage Account” to view entitlements.
  • Click the “Access Key” link on the left side menu
  • Click the “Create an Access Key” button.
  • Download the resulting file “cred.json”.

Note:  The resulting access key will enable all entitlements within your account.  If you have not yet obtained entitlements from the “TRY OR BUY” section above, you must do so before following these steps for generating your access key.


Host Setup

Ensure that the U50 board installed on the machine is flashed with the xilinx_u50_gen3x16_xdma_201920_3 shell, and XRT 2.8.743 is installed. Refer to Xilinx UG1370 document for instructions.

This application assumes your card is in slot "0". Moreover, the instructions in this section should be run as the root user or with sudo, and docker should be installed on the system.

2.1 Clone GitHub Repository for Xilinx Base Runtime

    git clone https://github.com/Xilinx/Xilinx_Base_Runtime.git && cd Xilinx_Base_Runtime

2.2 Run the Host Set Up Script

    ./host_setup.sh -v 2020.2 -p alveo-u50

2.3 Run the following set of commands in a terminal window to detect and export FPGA device information:

    wget https://raw.githubusercontent.com/Xilinx/Xilinx_Base_Runtime/master/utilities/xilinx_docker_setup.sh
source xilinx_docker_setup.sh

NOTE: Our docker container deployment has been tested on Ubuntu 18.04. It may work on other versions of Ubuntu and/or CentOS 7.x/8.x, as well, however has not been fully tested.


Application Execution

Enter the following commands in a terminal window to run the application:

3.1 Pull the Docker Image

    docker pull xilinxpartners/edgecortix_f200_time:release

3.2 Run the Docker Image

    docker run -it $XILINX_DOCKER_DEVICES -v /*path*/cred.json:/opt/edgecortix/cred.json xilinxpartners/edgecortix_f200_time:release /bin/bash

Replace *path* in the above command to the correct path for the cred.json file.

Description of command arguments:

  • -v /*path*/cred.json:/opt/edgecortix/cred.json - Map local cred.json dir : container dir
  • $XILINX_DOCKER_DEVICES - Variables set by the xilinx docker setup


Demo example

Comprehensive instructions to create and compile arbitrary neural networks and run them on DNA-F200 can be found at the following address:


As an example, the following instructions will download, compile and run the Resnet 50 script available from that repo:

    cd /opt/edgecortix/private-tvm/apps/mera_cpp/
wget https://raw.githubusercontent.com/Edgecortix-Inc/dna-IP-series/main/example/resnet_50.py
sed -i "s/\"arch\": 100/\"arch\": 200/" resnet_50.py
python resnet_50.py
mkdir build
cd build
cmake ..
./inference ../resnet50_deploy/


Inference Results

You should get an output similar to the following (the "Took 8.09 msec." shows the end-to-end inference latency):

    [22:50:16] /opt/edgecortix/private-tvm/apps/mera_cpp/inference.cpp:63: Loading json data...
[22:50:16] /opt/edgecortix/private-tvm/apps/mera_cpp/inference.cpp:69: Loading runtime module...

Found Platform
Platform Name: Xilinx
INFO: Reading /opt/edgecortix/dna.xclbin
Loading: '/opt/edgecortix/dna.xclbin'

[  info  ] 726   , DRM session 72AF1306F0B91163 created.
[22:50:19] /opt/edgecortix/private-tvm/apps/mera_cpp/inference.cpp:74: Loading parameters...
[22:50:19] /opt/edgecortix/private-tvm/apps/mera_cpp/inference.cpp:82: Loading input...
[22:50:19] /opt/edgecortix/private-tvm/apps/mera_cpp/inference.cpp:114: Warming up...
[22:50:19] /opt/edgecortix/private-tvm/apps/mera_cpp/inference.cpp:120: Running 100 times...
[22:50:20] /opt/edgecortix/private-tvm/apps/mera_cpp/inference.cpp:127: Took 8.09 msec.
[22:50:20] /opt/edgecortix/private-tvm/apps/mera_cpp/inference.cpp:47: max abs diff: 1.17549e-38
[22:50:20] /opt/edgecortix/private-tvm/apps/mera_cpp/inference.cpp:48: mean abs diff: 0
[22:50:20] /opt/edgecortix/private-tvm/apps/mera_cpp/inference.cpp:49: correct ratio: 1
[  info  ] 726   , DRM session 72AF1306F0B91163 stopped.