3D Rendering, Digit Recognition, Spam Filter and Face Detection
Rosetta is a set of realistic benchmarks for software programmable FPGAs.
5-point relative pose problem
This work presents an implementation to solve the 5-point relative pose problem accelerated on Field Programmable Gate Array (FPGA).
AMI for Hardware-accelerated RSA Operations
AMI for hardware-accelerated RSA 2048 bit key operations.
Accelerated Genomic Pipelines
This repository hosts the source code used for the tutorial on CAOS, SDAccel and AWS F1 at ICCD 2017 on November 5th in Boston (MA).
Acceleration of SHA256 on the AWS F1 instance using OpenCL.
Adaptive Bit Rate Video Transcoding Application
This document describes the Xilinx video transcoding system that can accelerate ABR transcoding from H.264 to HEVC, or from H.264 to VP9.
In memory NoSQL database to perform look-ups with the lowest latency (less than 1 microsecond) and the highest throughput.
BMP to JPEG
Description coming soon!
Bellman-Ford algorithm for solving single-source shortest paths (SSSP)
This repository contains multiple implementations of the Bellman-Ford algorithm for solving single-source shortest paths (SSSP).
Bigstream Hyper-acceleration Software
Bigstream Hyper-acceleration layer automates the process of acceleration for the users of big data platforms. It is comprised of compiler technology for software acceleration via native C++, and FPGA acceleration templates.
Binomial Options Model
Demonstrating the acceleration of the Cox, Ross and Rubenstein Binomial options pricing model using SDAccel and Xilinx Alveo against multi-threaded CPU.
BlackLynx High Speed Search
Supercharge search capabilities to render big data relevant now. BlackLynx technology combines high performance computing (accelerated CPUs and FPGAs) with standard interfaces and protocols to achieve high performance analytics.
BlackLynx Image and Video Edge Analytics
BlackLynx is a leader in providing heterogenous computing solutions and because there are distinct operational advantages of optimally implementing advanced heterogenous solutions. The diagram illustrates the combined benefits of including multiple high-performance computing capabilities (GPU and FPGA) in an architecture.Xilinx® Alveo™ Data Center accelerator cards and BlackLynx technology combine to maximize the potential of image and video analysis at the edge of the network.
CFD Kernels optimized for Xilinx Alveo
Set of highly optimized CFD kernels that leverage the speed and energy efficiency of Xilinx Alveo FPGA accelerator cards to create a high-performance platform for complex engineering analysis.
CTAccel Image Processing (CIP) Accelerator
CTAccel Image Processing (CIP) accelerator is an FPGA-based image processing acceleration solution that greatly improves the performance of image processing and image analytics by transferring computational workload from CPU to FPGA. CIP's powerful processing capabilities benefit data centers by increasing image processing throughput by 3-7x, reduce computational latency by 3x, and reduce TCO by 3x. CIP redefines data center image processing with state-of-the-art technologies which utilize massively data parallel algorithm to increase computational performance.
Circulare RNA idenfication acceleration
Circular RNAs are a widespread type of RNA in our genome that have been recently discovered to be correlated with many types of carcinogenesis and central neural system pathologies.
DRAGEN Complete Suite - Ultra-rapid analysis of Next Generation Sequencing - Exome
The DRAGEN Complete Suite (Exome) enables ultra-rapid analysis of Next Generation Sequencing (NGS) data for small data sets, such as whole exomes and targeted panels.
DRAGEN Complete Suite - Ultra-rapid analysis of Next Generation Sequencing - Genome
The DRAGEN Complete Suite (Genome) enables ultra-rapid analysis of Next Generation Sequencing (NGS) data for large data sets, such as whole genomes.
Deep-Learning Inference with Binarized Neural Networks
Image classification of Cifar10 dataset using the CNV network. Based on Xilinx public proof-of-concept implementation of a reduced-precision, Binarized Neural Network implemented in FPGA.
Descartes Efficient Speech Recognition Engine (using LSTM)
This is an end-to-end ASR (Automatic Speech Recognition) system with FPGA acceleration on AWS F1 by DeePhi.
DesignStart FPGA on Cloud: Cortex-M33 based platform
A complete reference platform for software development on Arm's cutting edge Cortex-M33 processor for secure IoT applications.
FPGA Accelerated HEIF-to-JPEG Transcoder, HEVC Decoder
Free version of FPGA HEVC decoder on AWS F1 instance.
FPGA Cloud Crypto
Napatech FPGA Cloud Crypto is an FPGA-based DPDK cryptodev PMD which serves as a showcase demonstrator for AES-128-GCM cryptography.
FPGA Distribution Platform
Accelize offers a DRM-powered distribution platform for FPGA-accelerated Apps and IP cores that boost revenue through instant, scalable and secure deployment to customers around the globe. The platform supports any CSP as AWS, Huawei, Alibaba, Nimbix or Xilinx Alveo boards for on-prem deployment.
FPGA Miner & Verilog Code for Mining (Tribus, Skunk, phi1612)
Example verilog / miner for crypto mining using AWS F1 instances.
FPGA based GZIP compression
This repository contains following applications targeting Amazon Web Services (AWS F1) FPGA architecture.
Falcon Accelerated Genomics Pipelines
Working in partnership with Xilinx, the Falcon Computing Genomics Accelerated Platform (FGAP) works seamlessly on local appliances with XBB or on the public cloud. On the cloud, the platform is currently available on FPGA instances for AWS, Huawei, and Alibaba Cloud.
Fletcher: A framework to integrate FPGA accelerators with Apache Arrow
A framework to integrate FPGA accelerators with Apache Arrow.
The GZIP accelerator provides an hardware-accelerated gzip compression up to 25X faster than CPU compression. Generated archives are compliant to the RFC 1952 GZIP File Format Specification
Go Language to FPGA Platform
Build custom, reprogrammable, low latency accelerators using software defined chips.
GraphSim is a graph based SSSP algorithm by ArtSim. It is a pre-configured, ready to run image for execution of Dijkstra's shortest path search algorithm on Amazon's FGPA-accelerated F1.
HEVC Encoder - V01
Using an F1 instance, offload HEVC encoding to an FPGA. This version of the NGCodec Encoder features ABR multi-channel encoding with a combined frame rate at 1080p60.
Hadoop Map-Reduce Accelerator
Contains FPGA based accelerators for sort and merge phases of Map-Reduce.
High Performance Monte Carlo Option Pricing Simulation
This repository includes F1-optimized implementations of four Monte Carlo financial models, namely.
InAccel's Accelerated Machine Learning
Accelerate your Apache Spark applications using Logistic Regression, K-means and alternating-least squares. AML is InAccel's accelerated machine learning library. It aims to maintain the practical and easy to use interface of other open source frameworks, i.e. of Apache Spark, and at the same time to accelerate the training part of machine learning models. Right now AML hosts all the required libraries to train your Logistic Regression and KMeans models, but it will be getting updates regularly adding support for more algorithms and features.
InTime Automated Optimization Software for FPGA Design
Description coming soon!
Machine Learning Suite for Inference (Tensorflow, Caffe and MXNet)
Xilinx's new Machine Learning suite enables users to easily evaluate, develop and deploy FPGA-accelerated inference using ready-to-run network models including application source.
Maxeler RTR (Real Time Risk)
Maxeler Real Time Risk (RTR) is a suite of Finance Risk tools and components, including Credit Value Adjustment (CVA), Margin Requirements (ISDA SIMM and CME Clearing) but also a full derivatives pricing library, driven by Bloomberg market data and the customer trades in FPML format.
Software infrastructure for running DFE acceleration on F1.
Memcached Database Server
Memcached is a high-performance in-memory object caching system, used by Facebook, Flicker, Wikipedia, and other high-traffic websites. Memcached acts as a caching layer between web servers and databases to decrease server response times. FPGA compute instances are now being deployed in datacenters to accelerate network-centric workloads. LegUp Computing offers a cloud-deployed Memcached using AWS EC2 F1 (FPGA) instances. With a single F1 instance, LegUp’s Memcached server achieves over 11M ops/sec, a 9× improvement over AWS ElastiCache, an AWS-managed CPU Memcached service. Our FPGA-accelerated Memcached server responds to network requests in under 300µs, a 9× improvement in latency over ElastiCache.LegUp's FPGA Memcached server is compatible with standard Memcached client APIs meaning no software changes. Simply launch LegUp’s Memcached instance on AWS and connect your web server. We also offer an on-premise solution for the datacenter with Xilinx Alveo Data Center accelerator cards.
Mipsology Zebra for Deep Learning Inference
Zebra eliminates the challenging task of programming and FPGA for DL inference. Zebra is easy to deploy and accommodates a wide range of Neural Networks and Frameworks.
NoLoad® CSP RocksDB
Eideticom’s NoLoad® Computational Storage Processor (CSP) deployed on Xilinx Alveo cards was used to accelerate the production key-value store RocksDB. The solution resulted in significant improvements in performance and efficiency when compared to a software-only solution.
OpenMP to FPGA
Description coming soon!
PERSEUS Plus is a unique video encoding technology that significantly enhances the quality and throughput of any standard encoder such as AVC/H.264, HEVC, VP9 and – in the future - AV1. Playback is supported on a broad range of devices as it leverages the hardware decoding capabilities of the underlying codec that are already present. When combined with Xilinx FPGA, PERSEUS provides the highest density encoding solution in the market enabling use cases such as live 4kp60 encoding on a single card and accelerating the throughput of a server by up to 4x compared to existing solutions. PERSEUS is a single board FPGA solution able to accelerate existing codec deployments, whether in software or in hardware or to run as a complete standalone encoding pipeline. The addition of PERSEUS to an existing transcoding farm increases throughput by up to 4x times, reducing operational costs and greatly increasing the viability of new services, such as UHDTV. PERSEUS is easily deployable as an additional software component to exiting workflows.
Postgress Database Acceleration, execute existing Postgres SQL queries
Xilinx's new data analytics acceleration stack enables users to easily evaluate FPGA-accelerated SQL query using Postgres.
Pre-Trade Risk Check System (PTRC)
Algo-Logic Systems delivers an industry leading Pre-Trade Risk Check (PTRC) solution that verifies Security and Exchange Commission Rule 15c3-5 compliance with sub-microsecond latency that is consistently lower than software-based systems. The system enables broker/dealers to forward stock market orders from client machines to exchanges with nearly no added delay nor jitter.With an easy to use and secure, Graphical User Interface (GUI), broker/dealers can easily configure a wide range of risk check parameters to ensure compliance and protection prior to execution. Pre-Trade Risk Checks and associated control actions are accelerated in the FPGA.
ProFAX: Hardware Acceleration of a Protein Folding Algorithm
Description coming soon!
Python-Based Matrix Operation Accelerator
Xilinx’s GEMX (General Matrix Operation) library provides a set of high performed engines for accelerating applications that heavily depend on matrix operations.
Quantum Chromodynamics (QCD) implementation
Quantum Chromodynamics is the theory of the strong interaction between quarks and gluons, the fundamental particles that make up composite particles such as the protons & neutrons.
R11F: Live broadcast quality MPEG-4 AVC/H.264 video encoder
Description coming soon!
Reconfigurable Engine for Automata Processing (REAPR)
REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications such as regular expressions.
SHA-3 and SHAKE Hashing Function
The SHA-3 and SHAKE accelerator provides hardware accelerated hashing functions compliant to NISTS’s FIPS 180-4 and FIPS 202 standards.
Skreens Personalized Streaming Video Engine
Skreens is the personalized streaming video engine enabling innovative visual experiences for industries including Broadcast, Enterprise Collaboration, Gaming, Security, and Digital Media. Skreens solution enables a single developer friendly workflow capable of decoding multiple content feeds, integrated machine learning models and third-party APIs (Watson, IFTTT), producing a powerful end-user experience with event-triggered content overlays all encoded at ultra-low latency. Skreens Streaming Video Engine provides the power of a next-gen production studio in the cloud or at the edge with Alveo™ U200 Acceleration Card.
This is a test implementation of the Smith-Waterman algorithm, specifically the ksw_extend function as implemented in BWA, using Xilinx Vivado High-Level Synthesis.
Standard Initial Margin Model (SIMM) calculation
The SIMM framework is based on first-order greeks to make it more computationally tractable than other methodologies such as Expected Historical VaR. Maxeler’s SIMM calculation product powered by Xilinx Alveo U200 provides an industry-proven risk analytics infrastructure. SIMM product splits naturally into the calculation of sensitivities, and the application of risk weights and aggregation. The Maxeler Risk Analytics library provides the framework for calculating greeks on CPUs as well as on Xilinx U200 Acceleration card. Initial margin requirements can be calculated directly from a portfolio of trades supplied in FpML format, or indirectly by supplying sensitivity values from external models (for example, a liability exposure to be hedged).
SumUp Analytics Nucleus Platform
SumUp Analytics’ Nucleus platform is a Xilinx FPGA-powered Real-Time text analytics SaaS algorithm used in identifying, extracting and analyzing critical information from unstructured text. The platform works seamlessly on local appliances leveraging Alveo™ U200 Accelerator Card or on AWS EC2 F1 instances. Nucleus is comprised of a Python/SDAccel hybrid library running on the Xilinx FPGAs for core analytics and distributed-CPU for peripheral analytics.
The TAR.GZ accelerator provides hardware-accelerated TAR and/or GZIP operation up to 25X faster than CPU equivalent. Generated TAR archives are POSIX compliant. Generated GZIP archives are compliant to the RFC 1952 GZIP File Format Specification.
TRNG - True Random Number Generator
The TRNG accelerator provides an hardware-accelerated True Random Number Generator that exploits electronic noise to provide random bytes.
Titan IC RXP for FPGA
Titan IC is delighted to announce a new technology collaboration with Xilinx to embed our industry-leading Regular Expression Processor (RXP) into the Xilinx SDAccel environment to enhance network security by significantly augmenting FPGA offload acceleration and freeing up CPU capacity. The latest SDAccel release offers developers a fully-flexible and highly-configurable security processing engine for high throughput networks that need to be scanned with complex security rules.
Ultra Fast Search and Replace for Data Analytics
The Ultra Fast Search & Replace for Data Analytics engine accelerates whole words Find/Replace operations in ASCII files.
VAVILOV Genomics Engine
Ultra fast NGS short read aligner, FASTQ to SAM.
VP9 Encoder - V01
An FPGA based real-time 1080p60 VP9 encoder featuring ABR multi-channel encoding with minimal CPU load.
Value Function Iteration Accelerator (VFI)
Value Function Iteration Accelerator - FPGA.
Visual Systems Integrator for FPGA and Embedded Development
Accelerate your embedded/FPGA development.
Vitesse Data Deepgreen DB
Vitesse Data Deepgreen DB is a scalable MPP data warehouse solution derived from the open source Greenplum Database Project and maintains 100% compatibility with the open source project. Deepgreen DB works seamlessly on local appliances or on public clouds. AWS F1 instances can be configured with up to 8 FPGA instances for a total of 64 vCPU and 976 GB of memory. Vitesse’s Data Deepgreen DB Solution is currently available on AWS EC2 F1 instances and Alveo U200 Acceleration Card.
Web Image Encoding, Optimized to enable faster and smaller images on the Web
This repository contains following applications targeting Amazon Web Services (AWS F1) FPGA architecture.
With the Xelera Analytics software for Virtex® Ultrascale+ FPGAs in the cloud and on Xilinx® AlveoTM Data Center accelerator cards, customers can use Apache Spark MLib in the usual way – without any knowledge about hardware accelerators – and benefit from 50x acceleration. This enables real-time business applications with advanced analytics.
|Supported Workload||Title||Vendor||Acceleration vs. CPU|
|Tools and Services||3D Rendering, Digit Recognition, Spam Filter and Face Detection||Cornell||N/A|
|Tools and Services||5-point relative pose problem||Politecnico di Milano||64x|
|Security||AMI for Hardware-accelerated RSA Operations||ZO Tech||N/A|
|Genomics||Accelerated Genomic Pipelines||Politecnico di Milano||N/A|
|Security||Accelerated SHA-256||Uppsala University||N/A|
|Video and Image Processing||Adaptive Bit Rate Video Transcoding Application||Xilinx||10x|
|Data Analytics||Algo-Logic KVS||Algo-Logic Systems Inc.|
|Video and Image Processing||BMP to JPEG||ALSE (Advanced Logic Synthesis for Electronics)||2x|
|High Performance Computing||Bellman-Ford algorithm for solving single-source shortest paths (SSSP)||Open-source||N/A|
|Data Analytics||Bigstream Hyper-acceleration Software||Bigstream Inc.||2x to 30x|
|Financial Computing||Binomial Options Model||Xilinx|
|Data Analytics||BlackLynx High Speed Search||BlackLynx|
|Machine Learning||BlackLynx Image and Video Edge Analytics||BlackLynx|
|Data Analytics||CFD Kernels optimized for Xilinx Alveo||byteLAKE s.c.||up to 4x|
|Video and Image Processing||CTAccel Image Processing (CIP) Accelerator||CTAccel Limited|
|Genomics||Circulare RNA idenfication acceleration||Politecnico di Milano||1.7x|
|Genomics||DRAGEN Complete Suite - Ultra-rapid analysis of Next Generation Sequencing - Exome||Illumina (Edico Genome)||90x|
|Genomics||DRAGEN Complete Suite - Ultra-rapid analysis of Next Generation Sequencing - Genome||Illumina (Edico Genome)||90x|
|Machine Learning||Deep-Learning Inference with Binarized Neural Networks||MLE||800x|
|Machine Learning||Descartes Efficient Speech Recognition Engine (using LSTM)||Xilinx||10x|
|Tools and Services||DesignStart FPGA on Cloud: Cortex-M33 based platform||Arm Ltd||N/A|
|Video and Image Processing||FPGA Accelerated HEIF-to-JPEG Transcoder, HEVC Decoder||Pathpartner||N/A|
|Security||FPGA Cloud Crypto||Napatech||N/A|
|FPGA Distribution Platform||Accelize S.A.S.|
|Tools and Services||FPGA Miner & Verilog Code for Mining (Tribus, Skunk, phi1612)||Open-source||N/A|
|Compression||FPGA based GZIP compression||Xilinx||2.3x|
|Genomics||Falcon Accelerated Genomics Pipelines||Falcon Computing Solutions, Inc.|
|Data Analytics||Fletcher: A framework to integrate FPGA accelerators with Apache Arrow||Delft University of Technology||N/A|
|Tools and Services||Go Language to FPGA Platform||reconfigure.io||100x|
|Video and Image Processing||HEVC Encoder - V01||NGCodec||N/A|
|Data Analytics||Hadoop Map-Reduce Accelerator||BigZetta||10x|
|Financial Computing||High Performance Monte Carlo Option Pricing Simulation||Politecnico Di Torino||42x-540x|
|Data Analytics||Hyperon - HW Acceleration for Big-Data Applications||Grovf Inc||50X|
|Machine Learning||InAccel's Accelerated Machine Learning||InAccel LLC|
|Tools and Services||InTime Automated Optimization Software for FPGA Design||Plunify||N/A|
|Machine Learning||Machine Learning Suite for Inference (Tensorflow, Caffe and MXNet)||Xilinx||10x|
|Financial Computing||Maxeler RTR (Real Time Risk)||Maxeler Technologies Inc.|
|Tools and Services||MaxelerOS AMI||Maxeler Technologies Inc.||N/A|
|Data Analytics||Memcached Database Server||LegUp Computing Inc.|
|Machine Learning||Mipsology Zebra for Deep Learning Inference||Mipsology SAS|
|Genomics||NGS Reference Genome Assembly||Deneb Genetics||100x||
|Compression||NoLoad® CSP RocksDB||Eidetic Communications Inc.|
|Tools and Services||OpenMP to FPGA||Hardcloud.org||N/A|
|Video and Image Processing||PERSEUS||V-Nova Ltd|
|Data Analytics||Postgress Database Acceleration, execute existing Postgres SQL queries||Xilinx||2x-3x|
|Financial Computing||Pre-Trade Risk Check System (PTRC)||Algo-Logic Systems Inc.|
|High Performance Computing||ProFAX: Hardware Acceleration of a Protein Folding Algorithm||NECST Laboratory||1.6x|
|High Performance Computing||Python-Based Matrix Operation Accelerator||Xilinx||N/A|
|High Performance Computing||Quantum Chromodynamics (QCD) implementation||Maxeler Technologies Inc.||N/A|
|Video and Image Processing||R11F: Live broadcast quality MPEG-4 AVC/H.264 video encoder||Integrated Device Technology, Inc. (IDT)||N/A|
|Tools and Services||Reconfigurable Engine for Automata Processing (REAPR)||University of Virginia||100x|
|Security||SHA-3 and SHAKE Hashing Function||Silex Insight||6x|
|Video and Image Processing||Skreens Personalized Streaming Video Engine||Skreens|
|Genomics||Smith-Waterman Algorithm||High-Performance Low-Power Lab||N/A|
|Financial Computing||Standard Initial Margin Model (SIMM) calculation||Maxeler Technologies Inc.|
|Machine Learning||SumUp Analytics Nucleus Platform||SumUp Analytics|
|Security||TRNG - True Random Number Generator||Secure IC||N/A|
|Security||Titan IC RXP for FPGA||Titan IC Systems Ltd|
|Data Analytics||Ultra Fast Search and Replace for Data Analytics||Axonerve||6000x|
|Genomics||VAVILOV Genomics Engine||Deneb Genetics||100x|
|Video and Image Processing||VP9 Encoder - V01||NGCodec||N/A|
|Tools and Services||Value Function Iteration Accelerator (VFI)||Solutions for Economists||N/A|
|Tools and Services||Visual Systems Integrator for FPGA and Embedded Development||SystemView||N/A|
|Data Analytics||Vitesse Data Deepgreen DB||Vitesse Data Inc|
|Video and Image Processing||Web Image Encoding, Optimized to enable faster and smaller images on the Web||Xilinx||6.5x-14.2x|
|Data Analytics||Xelera Analytics||Xelera Technologies|