The Kintex® UltraScale™ FPGA Acceleration Development Kit is an excellent starting point for hyperscale application developers. This kit is based on a production-ready PCI card accessible in the cloud with the frameworks, libraries, drivers and development tools to support easy application programming with OpenCL, C, C++ through SDAccel. Get started in the cloud, with this physical kit or both to move through development with Xilinx and go to production with one of Xilinx’s ecosystem partners.
Device Support: Kintex UltraScale
|Vivado Design Suite: Design Edition||The Xilinx Vivado® Design Suite is a revolutionary IP and System Centric design environment built from the ground up to accelerate the design for all programmable devices.||Node locked and device-locked to the XCKU115 FPGA, with one year of updates.
Supports partial reconfiguration
|SDAccel Development Environment||SDAccel is a development environment for OpenCL applications targeting PCIe®-based Xilinx FPGA accelerator cards. This environment enables concurrent programming of the system processor and the FPGA logic without the need for RTL design experience.||Node locked and device-locked to the XCKU115 FPGA, with one year of updates.|
|Partial Reconfiguration||Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading partial bit files while the remaining logic continues to operate without interruption. Xilinx Partial Reconfiguration technology allows designers to change functionality of the accelerator board on the fly, eliminating the need to fully reconfigure and re-establish PCIe links while reloading.||Node locked and device-locked to the XCKU115 FPGA, with one year of updates.|
|DDR4 SDRAM Controller||DDR4 SDRAM controller is a free IP core in the Vivado IP Catalog.||No-Charge IP|
|DMA for PCI Express (PCIe) Subsystem||The Xilinx® LogiCORE™ DMA for PCI Express (PCIe) implements a high performance, configurable Scatter Gather DMA for use with the PCI Express 3.x integrated block. The IP provides an optional AXI4 or AXI4-Stream user interface.||No-charge IP|
|Xilinx SmartConnect Technology||The Xilinx SmartConnect Technology enables unprecedented levels of performance for the UltraScale+™ device portfolio, by solving the system interconnect bottlenecks on high density, multi-million system logic cell designs.||No-charge IP|
|SDAccel Platform Reference Design for Custom Board Support||SDAccel projects are compiled against a target platform. The SDAccel Platform Reference Design is the combination of board and hardware/software infrastructure components on which the kernels of an OpenCL application are executed. This reference design is intended to be used as a starting point to help platform developers add SDAccel support for their custom PCIe boards.