Xilinx All Programmable Abstractions improve productivity of hardware designers and empower systems and software developers to directly leverage All Programmable FPGA, SoCs, and 3D ICs. Xilinx and its ecosystem Alliance members now support a combination of software, model, platform, and IP- based design environments. These software and system level abstractions complement hardware focused IP integration and C-based design abstractions that have already proven to accelerate development of complex FPGAs and SoCs.
Xilinx SDx Development Environment
SDx™ is a family of development environments for systems and software engineers. SDx enables developers with little or no FPGA expertise to use high level programming languages to leverage the power of programmable hardware with industry standard processors on or off chip.
Xilinx C-based IP generation with Vivado High-Level Synthesis for Hardware Engineers
Hardware abstraction with QEMU and Cadence
To accelerate software development of the Zynq®-7000 All Programmable SoC and MicroBlaze™ processor, Xilinx has developed a Quick Emulator (QEMU) open source virtual machine that emulates the system hardware/software interfaces. The earlier software development results in higher productivity, and continuous hardware/software integration validation. Get more information and to download the QEMU models for Zynq and MicroBlaze.
In addition Xilinx has partnered with Cadence® Design Systems to provide the Virtual System Platform for the Xilinx Zynq-7000 All Programmable SoC. Together with the Xilinx Software Development Kit (SDK), the first application IDE to deliver true homogenous and heterogeneous multiprocessor design and debug, using these virtualization environments, design teams can shave months off of system development schedules. Also you can get more information on the Cadence Virtual System Platform.
Model-Based Design with MathWorks Simulink and System Generator for DSP
MATLAB™ and Simulink™ enable design, simulation, and verification of applications. Now with the latest release, designs can be targeted to the Zynq®-7000 All Programmable SoC. MathWorks offers a guided workflow that allows users to partition an algorithm into HW and SW then generate VHDL® code for the programmable logic using HDL Coder™ and C code for the ARM processor using Embedded Coder™. Learn more about this new level of automation for MathWorks model-based designs.
The Vivado® Design Suite System Edition includes System Generator for DSP, the industry's leading high-level tool for creating production-quality DSP algorithms in a fraction of time compared to traditional RTL. System Generator accelerates the development of highly parallel systems by empowering developers to seamlessly integrate arithmetic functions, SmartCore™ IP, custom RTL, C-based Vivado HLS blocks and automatic code generation with the industry’s most advanced All Programmable system modeling from MATLAB and Simulink. Get more information on Vivado Design Suite and System Generator for DSP.
Platform-based Design with National Instruments RIO Platforms and LabVIEW
Embedded system designers use LabVIEW and National Instruments® (NI) re-configurable I/O (RIO) hardware to abstract the complexity of traditional RTL design and avoid the time consuming tasks of building an operating system, drivers, and middleware for deployment targets.
National Instruments created a platform-based approach to embedded design that includes off the shelf re-configurable hardware and intuitive graphical programming. With a single-click, the NI LabVIEW 2013 development environment can compile, debug, and deploy applications written for processor or programmable logic on NI targets. This development environment currently supports multiple Xilinx All Programmable devices. NI chose Xilinx All Programmable SoCs and FPGAs for the RIO computing core, platform of over 60 deployable targets. For information about this flow please visit www.ni.com/xilinx