SuperVessel is a first-of-its-kind open access cloud service that acts as a virtual R&D engine for application developers, system designers, and academic researchers to create, test and pilot solutions for emerging applications including deep analytics, machine learning and the Internet of Things.
The Xilinx SDAccel™ Development Environment is a complete software-defined Integrated Development Environment (IDE) that enables developers to compile, profile, debug and deploy FPGA-based acceleration. The combination of SuperVessel, IBM POWER architecture, the SDAccel Development Environment, and Xilinx FPGA accelerator boards provide application developers with a high throughput, high availability cloud-based platform to develop and execute the compute intensive applications.
Access to SuperVessel will be available May 2016. Sign up here to receive priority notification when registration opens for SDAccel on the SuperVessel Cloud.
Getting Started with the SDAccel Development Environment
SDAccel is the Xilinx development environment for C, C++ and OpenCL applications targeting PCIe accelerators cards built using Xilinx FPGAs. This environment allows an application developer to create a software accelerator using industry standard APIs and programming paradigms common to heterogeneous parallel systems.
To learn more about the SDAccel Development Environment, start by watching introduction videos located on the SDAccel page.
To learn about how to create accelerators for the FPGA fabric, look at the examples provided by Xilinx and ecosystem partners at https://github.com/Xilinx/SDx/tree/master/Examples/SDAccel
Getting Started with SuperVessel
The SuperVessel cloud is freely available to all researchers and developers looking to learn about the combination of the IBM POWER processor family and FPGA-based accelerators. In order to get the best results from the SuperVessel cloud, the developer should keep the following in mind:
- FPGA-based applications are characterized by parallelization and by having the application performance bound limited by compute instead of data transfer
- Accelerator performance is directly proportional to how the workload is expressed. For best performance accelerator code needs to be optimized for the FPGA architecture just as in the case of CPU or GPU accelerators
- FPGA accelerators are executed from precompiled accelerators. On the fly compilation of accelerators from within the end user application is not supported.