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Timing Driven Place and Route

Xilinx invented Timing-Driven Place and Route for programmable logic. In the ISE® Design Suite, when you specify timing requirements for critical paths, performance is dramatically improved through tools such as Timing Analyzer and Constraints Editor with TimeSpecs FPGA Editor. Timing Driven Place and Route provides the most advanced technology to help your designs meet timing specifications much more quickly than traditional methods.

  • Continued algorithmic innovations deliver superior quality of results (QoR)
  • Physical Synthesis creates a physically optimized design after synthesis that meets design performance goals in a single pass
  • Cross-probing makes it easy to see the critical timing paths in your desig
  • Timing Improvement Wizard identifies why a path is not meeting timing and makes suggestions for improvement
  • HDL Advisor suggests changes in HDL source to improve the speed of your design

SmartGuide minimizes implementation differences between two versions of the same design minimizing changes on a previously successful implementation where only minimal changes are being made.

SmartGuide can be enabled with nominal changes to an existing design flow. Faster runtimes will be realized and timing will be preserved for small design changes that are not on a critical path. The result is significantly faster implementation times with less risk, late in the project.

SmartXplorer automatically help you find the ideal design results through multiple implementation runs using different place and route settings and constraints.

SmartXplorer leverages distributed processing to manage multiple implementation runs in an effort to achieve these ideal design results. Through parallel efforts, SmartXplorer investigates the results of implementation runs to close in on optimal settings in far less time. SmartXplorer can be used make better use of multiple compute platforms to more quickly achieve timing closure or in a single platform environment. SmartXplorer, in combination with retiming in synthesis, help designers improve performance by an average 10%.

SmartXplorer is enabled from within the properties of the project properties. Using user constraints together with optimization strategies, such as Global Optimization, Timing Driven Packing and Placement, Register Duplication, and Cost Tables, SmartXplorer implements the design in multiple ways to meet desired performance goals.