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Vivado Hardware Debug

Vivado Debug offers a variety of solutions to help users debug their designs easily, quickly, and more effectively. These solutions consist of tools, IPs, and flows that enable a wide range of capabilities from logic to system level debug while the user design is running in hardware.

In addition, Vivado provides a unified design environment that enables you to perform different debug tasks within the same IDE in which interfaces look consistent and features communicate well between each other.

What’s New in 2016.3

Platform/Logic Debug – enhanced interface-level debug flow in IP Integrator  (IPI):

  • New ‘System ILA’ core available in IPI, which allows selection of multiple interfaces and signals for debug
  • Designer assistance in IPI to make it easy to enable/disable debug on various interface and signal connections
  • Automatic propagation of AXI interfaces information throughout the implementation flow
  • Automatic detection of events on AXI channels in waveform viewer


Logic Analyzer GUI

  • Ease of use improvements for Trigger Setup/Capture Window
  • GUI support for creation of new probes based on existing ILA probes after programming the device


Remote Debug
– enhanced debug flow for XVC:

  • Support for different use cases with or without access to physical JTAG pins
  • New ‘Debug Bridge’ IP, which connects to debug cores to interact with XVC server running on an SoC
  • Support for AXI interfaces such as PCIe or Ethernet to communicate with XVC server


Transceiver Debug

  • New ‘In-system IBERT’ IP, which utilizes user data to plot eye scan of GTH/GTY in UltraScale™/UltraScale+™ devices
  • Enhanced eye scan plotting in Serial I/O Analyzer

Tools & Features

As part of Vivado IDE, Hardware Manger facilitates device programming and debug after the user generates a bitstream file. Hardware Manger allows you to connect and program hardware targets containing one or more FPGA devices and then interact with the debug IPs within the FPGA designs via the Tcl console or a number of GUI interfaces including Logic Analyzer, Serial I/O Analyzer, and Memory Calibration Debug tool.

Feature Highlights:

  • Device programmer for FPGA, configuration memory devices, eFUSE AES key/registers
  • Access to System Monitor (SYSMON) - ADC & on-chip sensors
  • Scripting support via Tcl console for debug automation
  • Remote debugging over network
  • Support for Xilinx Virtual Cable (XVC)

Key Documents

Name File Size Modified Date
Vivado Programming and Debugging User Guide (UG908) 5 MB 03/31/2015
Tcl Command Reference Guide (UG835) 10 MB 03/31/2015

QuickTake Video Tutorials

Vivado provides various debug IP and tool features that enable you to easily perform in-system logic debugging of your implemented design.

Using HDL instantiation or netlist insertion, you can add debug IP to your design. Available logic debug IP include:

  • ILA – basic/advanced trigger and capture of internal signals
  • VIO – simple monitoring and driving of internal signals
  • JTAG-to-AXI – transaction level interaction with AXI interfaces within a system via Tcl

After device programming, you then interact with these IP by using the Vivado Logic Analyzer tool. It offers customizable Dashboards to display all status and control information pertaining to a given debug IP.

Feature Highlights:

  • Intuitive debug flows & methodology
    • Netlist insertion support for ILA via Tcl & GUI (Setup Debug Wizard, Debug Window)
    • HDL instantiation support for ILA, VIO, & JTAG-to-AXI
    • Support for identifying debug nets in RTL, GUI, XDC
    • Support for preserving debug nets during synthesis & implementation
  • Flexible analysis tool – Vivado Logic Analyzer
    • Customizable dashboards to interact with ILA/VIO
    • Easy setup for taking measurements and capturing data
    • Configurable Waveform viewer to analyze captured data

Key Documents

QuickTake Video Tutorials

Name Duration Release Date
Programming and Debugging Design in Hardware 08:08 min 08/01/2012
Using New Dashboards in Vivado Logic Analyzer 09:37 min 04/02/2015
Using JTAG to AXI Master 05:37 min 10/02/2013
Inserting Debug Cores into the Design 07:41 min 08/01/2012
Debugging at Device Startup 13:27 min 11/18/2014

Vivado offers you a fast and easy method to debug and optimize FPGA transceivers. This solution includes a customizable debug IP (IBERT) and Vivado Serial I/O Analyzer tool. Used together, you can take bit-error ratio (BER) measurements on multiple channels, perform 2D eye scan, and adjust transceiver parameters in real-time while your serial I/O channels interact with the rest of the system.

Designed for PMA evaluation and demonstration of transceivers, IBERT also includes data pattern generators and checkers as well as access to transceivers DRP ports. Once IBERT is implemented within the FPGA, Vivado Serial I/O Analyzer interacts with the IP and allows you to create links (analogous to a channel on a board) and analyze the margin of the links by running scans and viewing the results graphically.

Feature Highlights:

  • RX Margin Analysis with different scan algorithms
  • Link-based analyzer with support for creating custom links
  • Link auto-detection
  • Link sweep automation for running multiple scan with different settings
  • Auto sweep of transceiver parameters in real-time

Key Documents

QuickTake Video Tutorials

Name Duration Release Date
Using Vivado Serial IO Analyzer
07:40 min 08/09/2013

Memory Calibration Debug tool allows you to quickly debug calibration or data errors in UltraScale memory interfaces (DDR4/3, RLDRAM3, QDRII+). You can always view and analyze core configuration, calibration status, and data margin of the memory interfaces at any time throughout operation in hardware.

To debug calibration errors, you can use the displayed information to determine which stage of calibration is failing, which byte/nibble/bit is causing the failure, and how the calibration algorithm is failing. In addition, you can analyze the available read margin during normal operation. Observing the margin on each bit helps one determine if there are some signal integrity or board issues on certain data bits.

Feature Highlights:

  • Failure detection of various calibration stages
  • Visualization of the read calibration margins
  • Export capability of calibration results

Key Documents