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Vivado Hardware Debug

Vivado Debug offers a variety of solutions to help users debug their designs easily, quickly, and more effectively. These solutions consist of tools, IPs, and flows that enable a wide range of capabilities from logic to system level debug while the user design is running in hardware.

In addition, Vivado provides a unified design environment that enables you to perform different debug tasks within the same IDE in which interfaces look consistent and features communicate well between each other.

What’s New in 2017.1

Platform Debug – Transaction-level debugging for AXI interfaces in IP Integrator (IPI):

  • Support for AXI interfaces transaction-level debug at runtime (waveform window)
    • Shows transaction rows for issued AXI read/write transfers
    • Shows events for various AXI interface channels

Partial Reconfiguration Debug

  • Support for debug within the static and/or any number of the reconfigurable portions of the design
  • Ease of use for bitfile management at runtime

XVC over PCIe – remote debugging capability especially useful for datacenter applications:

  • Easy way to debug through PCIe interface without access to physical JTAG pins
  • New mode for ‘Debug Bridge’ IP to connect to PCIe IP and debug cores
  • New XVC server and PCIe driver for host to interact with the design running in hardware
  • Reference solution offered in the PCIe IP example design

Transceiver Debug

  • New advanced features (e.g. insertion loss) added to ‘IBERT’ IP generation to help customize the IP similar to GT Wizard
  • Support for 1D bathtub eye scan plotting in Serial I/O Analyzer

Tools & Features

As part of Vivado IDE, Hardware Manger enables user to program the device and debug the design after bitstream generation. Using Hardware Manger, users connect and program hardware targets containing one or more FPGA devices and then interact with debug IPs in designs via Tcl or GUI interfaces including Logic Analyzer, Serial I/O Analyzer, and Memory Calibration Debug.

Feature Highlights:

  • Device programmer for FPGA, configuration memory devices, eFUSE AES key/registers
  • Access to System Monitor (SYSMON) - ADC & on-chip sensors
  • Tcl scripting support for debug automation
  • Basic remote debugging over network via hw_server
  • Advanced remote debugging using Xilinx Virtual Cable (XVC)

For additional information, documentation, and video tutorials go to:
Design Hubs > Vivado Design Suite – Programming and Debug

Vivado Lab Edition – HW Manager and all of its features are available as part of the Vivado Design Edition or as a standalone installation package called Vivado Lab Edition. This edition has a small install package size (~1GB) with a small disk footprint (~2.4GB) after installation. It is typically used for lab environment settings that have limited disk space, memory, or connectivity. For more information, go to Vivado downloads and installation page.

Remote Debugging – Vivado offers a variety of ways users can remotely debug their designs without physically connecting to the JTAG pins of an FPGA. These methods are mainly based on the Xilinx Virtual Cable (XVC) technology as well as specialized debug cores such as Debug Bridge IP. The hardware and software components integrated as a complete solution enable you to remotely debug your designs through interfaces such as Ethernet or PCIe without the need to access the JTAG pins of the target FPGAs. For more information, go to Xilinx Virtual Cable page.

Vivado provides various debug IP and tool features that enable you to easily perform in-system logic debugging of your implemented design.

  • ILA – used for triggering on events and capturing the data from internal signals
  • System ILA - used for transaction-level debug of AXI interfaces
  • VIO – used for monitoring and driving internal signals
  • JTAG-to-AXI – used for direct interaction with AXI interfaces via Tcl

Different debug flows in the tool enable you to easily add or set up these debug IPs within your design at your preferred stage of the design cycle.

After the device is programmed, you then interact with these IPs in HW Manager by using the Vivado Logic Analyzer tool. Different dashboards within the Logic Analyzer tool display the status and control the operation of logic debug IPs.

Feature Highlights:

  • Intuitive and productive debug flows & methodology
    • Support for identifying debug nets in RTL, GUI, XDC
    • Netlist insertion support for adding an ILA to a design after synthesis
    • HDL instantiation support for all debug IPs
    • Support for advanced debug flows (ECO, Incremental) for more debug turns per day
    • Support for preserving debug nets/interfaces during synthesis & implementation
    • IPI debug flow for transaction-level debug of interfaces

  • Flexible analysis tool – Vivado Logic Analyzer
    • Customizable dashboards to interact with ILA/VIO
    • Easy setup for taking measurements and capturing data
    • Configurable Waveform viewer to analyze captured data

For additional information, documentation, and video tutorials go to:
Design Hubs > Vivado Design Suite – Programming and Debug

AXI Transaction-level Debug – within Vivado IP Integrator (IPI) tool, it is also possible to debug AXI interfaces at transaction-level. IPI makes it easy to debug various interface and signal and provides automation to connect these interfaces to System ILA. Interface information is then preserved throughout the implementation flow and at runtime, Waveform window shows all transaction and events for AXI interfaces based on the issued AXI read/write transfers.

Vivado offers you a fast and easy method to debug and optimize FPGA transceivers. This solution includes a customizable debug IP (IBERT) and Vivado Serial I/O Analyzer tool. Used together, you can take bit-error ratio (BER) measurements on multiple channels, perform 1D/2D eye scans, and adjust transceiver parameters in real-time while your serial I/O channels interact with the rest of the system.

Designed for PMA evaluation and demonstration of transceivers, IBERT also includes data pattern generators and checkers as well as access to transceivers DRP ports. Once IBERT is implemented within the FPGA, Vivado Serial I/O Analyzer interacts with the IP and allows you to create links (analogous to a channel on a board) and analyze the margin of the links by running scans and viewing the results graphically.

Feature Highlights:

  • RX Margin Analysis with different scan algorithms
  • Link-based analyzer with support for creating custom links
  • Link auto-detection
  • Link sweep automation for running multiple scan with different settings
  • Auto sweep of transceiver parameters in real-time

For additional information, documentation, and video tutorials go to:
Design Hubs > Vivado Design Suite – Programming and Debug

In-System IBERT – this IP is intended for evaluating & monitoring of UltraScale/UltraScale+ transceivers within a user design. It is capable of utilizing the actual data from the user design running on the FPGA to plot the eye scan of transceivers. It is available in IP catalog as a standalone IP to be used alongside transceiver-based Xilinx IPs. Users can also automatically add this IP to the GT Wizard example design as well as PCIe Gen3 IP.

Memory Calibration Debug tool allows you to quickly debug calibration or data errors in UltraScale/UltraScale+ memory interfaces (DDR4/3, RLDRAM3, QDRII+, and LPDDR3). You can always view and analyze core configuration, calibration status, and data margin of the memory interfaces at any time throughout operation in hardware.

To debug calibration errors, you can use the displayed information to determine which stage of calibration is failing, which byte/nibble/bit is causing the failure, and how the calibration algorithm is failing. In addition, you can analyze the available read margin during normal operation. Observing the margin on each bit helps one determine if there are some signal integrity or board issues on certain data bits.

For additional information, look at US/US+ Memory Interfaces Product Guide (PG150):
Design Hubs > Memory Interfaces (DDR3/DDR4, RLDRAM 3, QDRII+)