Advanced algorithms used today in wireless, medical, defense, and consumer applications are more sophisticated than ever before. Vivado® High-Level Synthesis included as a no cost upgrade in all Vivado HLx Editions, accelerates IP creation by enabling C, C++ and System C specifications to be directly targeted into Xilinx programmable devices without the need to manually create RTL. Supporting both the ISE® and Vivado design environments Vivado HLS provides system and design architects alike with a faster path to IP creation by :
Vivado HLS supports older architectures specific to ISE Design Suite and installs automatically as part of the Vivado HLx Editions.
The following libraries are included with Vivado HLS:
|Arbitrary Precision Data Types||Integer and fixed-point (ap_cint.h, ap_int.h and systemc.h)
|HLS Stream||Models for streaming data structures. Designed to obtain best performance and area (hls_stream.h)|
|HLS Math||Extensive support for the synthesis of the standard C (math.h) and C++ (cmath.h) math libraries. The support includes floating point and fixed-point functions: abs, atan, atanf, atan2, atan2, ceil, ceilf, copysign, copysignf, cos, cosf, coshf, expf, fabs, fabsf, floorf, fmax, fmin, logf, fpclassify, isfinite, isinf, isnan, isnormal, log, log10, modf, modff, recip, recipf, round, rsqrt, rsqrtf, 1/sqrt, signbit, sin, sincos, sincosf, sinf, sinhf, sqrt, tan, tanf, trunc|
|HLS Video||Video library to implement several aspects of modeling video design in C++ with video Functions, specific data types, memory line buffer and memory window (hls_video.h). Through a data type hls::Mat, Vivado HLS is also compatible with existing OpenCV functions: AXIvideo2cvMat, AXIvideo2CvMat, AXIvideo2IplImage, cvMat2AXIvideo, CvMat2AXIvideo, cvMat2hlsMat, CvMat2hlsMat, CvMat2hlsWindow, hlsMat2cvMat, hlsMat2CvMat, hlsMat2IplImage, hlsWindow2CvMat, IplImage2AXIvideo, IplImage2hlsMat, AbsDiff, AddS, AddWeighted, And, Avg, AvgSdv, Cmp, CmpS, CornerHarris, CvtColor, Dilate, Duplicate, EqualizeHist, Erode, FASTX, Filter2D, GaussianBlur, Harris, HoughLines2, Integral, InitUndistortRectifyMap, Max, MaxS, Mean, Merge, Min, MinMaxLoc, MinS, Mul, Not, PaintMask, PyrDown, PyrUp, Range, Remap, Reduce, Resize, Set, Scale, Sobel, Split, SubRS, SubS, Sum, Threshold, Zero|
|HLS IP||Integrate the LogiCORE IP FFT and FIR Compiler (hls_fft.h, hls_fir.h, ap_shift_reg.h)|
|HLS Linear Algebra||Support for the following functions: cholesky, cholesky_inverse, matrix_multiply, qrf, qr_inverse, svd (hls_linear_algebra.h)|
|HLS DSP||Support for the following functions: atan2, awgn, cmpy, convolution_encoder, nco, qam_demod, qam_mod, sqrt, viterbi_decoder (hls_dsp.h)
For FPGA designers looking to shorten design time and ensure scalability and re-use, Xilinx provides a comprehensive suite of solutions ranging from C-based design abstractions to IP plug-and-play to address bottlenecks in hardware development, system-level integration, and implementation.
Jump start your installation and design with the following videos.
Learn more about Vivado by selecting the following design flows.