The Vivado® Design Suite provides an array of design entry, timing analysis, hardware debug, and simulation capabilities all encompassed in a single state of the art integrated design environment (IDE). This flow enables both the integrated and enterprise verification needs for all supported simulators.
Vivado enables behavioral, post-synthesis and post-implementation (functional or timing) simulations for the fully integrated Vivado Simulator and 3rd party HDL simulators. Time spent on simulation early in the design cycle helps identify issues early and significantly reduces turnaround times compared to later stages of the flow.
To aid flexibility in user verification environments, Vivado provides support for both an integrated environment as well as provides scripts to use with external verification setups.
What’s New in Vivado Design Suite 2017.1
Simulation Flow
- Support for SystemVerilog package libraries in launch simulation and export simulation flow
- Ability for users to have finer control of compilation and simulation scripts using the new Pre and Post TCL script method
Simulation Performance
- Simulation model tuning for additional IP simulation performance
- Accelerated UltraScale PCIe® simulation
- Supported Simulators
- Multiple Simulations
The Vivado IDE supports all major simulators in integrated mode for interactive simulation users and script mode for advanced verification engineers.
| Vendor | Simulators | Interactive | Scripts |
|---|---|---|---|
| Aldec | Active-HDL, Riviera-PRO |
 |
|
| Cadence | Incisive Enterprise Simulator (IES) | |
|
| Mentor Graphics | ModelSim, Questa Advanced Simulator | |
|
| Synopsys | VCS | |
|
| Xilinx | Vivado Simulator | |
|
Feature highlights:
- Vivado provides the ability to compile simulation libraries for the supported simulators in the users’ environment to enable re-use of compiled libraries.
- Ability to simulate and verify design integrity at different stages of the design process
- Behavioral simulation
- Post-synthesis functional and timing simulation
- Post-implementation functional and timing simulation
- Portable integrated simulation environment
- Unified simulation integration using consistent 3 step process (compile, elaborate, simulate) for all simulators
- Simulation script generation for enterprise 3rd party simulators
- IP generation step creates simulation scripts
- Users enabled with generation of scripts to incorporate into user environments
The Vivado integrated design environment (IDE) provides users with the ability to explore multiple simulation strategies using simulation sets. The simulation sets allows users to manage the verification process within the Vivado IDE and creates different simulation flows depending on the verification needs.
The Vivado integrated design environment (IDE) provides users with the ability to explore multiple simulation strategies using simulation sets. The simulation sets allows users to manage the verification process within the Vivado IDE and creates different simulation flows depending on the verification needs.
Feature highlights:
- Flexible simulation environment to explore different simulation strategies
- Different Verilog defines
- Change sources (testbench, header files…)
- Compare multiple simulations – side by side
- Run behavioral and post-synthesis simulation simultaneously
- Organize simulation flows
- Separate simulation sets can be created for module level simulation and system level simulation
Key Documents
| Name | File Size | Modified Date |
|---|---|---|
| Vivado Design Suite Tutorial: Logic Simulation | 2 MB | 04/05/2016 |
| ISE to Vivado Design Suite Migration Guide | 1 MB | 04/05/2016 |
| Vivado Design Suite Tutorial: Logic Simulation | 2 MB | 04/05/2016 |
| Vivado Design Suite Tcl Command Reference Guide | 10 MB | 04/05/2016 |
| Vivado Design Suite User Guide: Release Notes, Installation, and Licensing | 4 MB | 04/12/2016 |