Vivado Simulator

Vivado® Simulator is a feature-rich, mixed-language simulator that supports Verilog, SystemVerilog and VHDL language. Vivado Simulator is included in all Vivado HLx Editions at no additional cost. It does not have a design size, instances or line limitation and it allows to run unlimited instances of mixed-language simulation using single Vivado license.

Vivado Simulator supports both Windows® and Linux operating system with powerful debugging features that are aimed to address the verification needs of Xilinx customers.

Supported Features

Vivado Simulator is a hardware description language (HDL) event-driven simulator that supports behavioral and timing simulation for single language and mixed language designs.

Feature highlights:

  • SystemVerilog (Including constraint randomization and functional coverage)
  • Verilog 2001
  • VHDL 93 and VHDL 2008
  • UVM 1.2
  • Standard Delay Format (SDF) 3.0 for timing simulation
  • Switching Activity Interchange Format (SAIF) for power analysis
  • Value Change Dump (VCD) support
Waveform Debug

Vivado Simulator has a powerful and advanced waveform viewer that supports digital and analog waveform generation. Vivado leverages the same waveform viewer interface for the simulator, hardware debug and system generator environments to provide a consistent and powerful interface to all users.

The waveform viewers’ cross probing feature allows users to easily traverse logic from waveform to text editor and vice versa making the debug process seamless.

Feature highlights:

  • Analog waveform viewer
    • Visualize digitally encoded analog signals (DSP, AMS)
  • Abstract signals for easy debug
    • Virtual busses
    • Signal groupings
    • Signal dividers
  • Enables to work with comfortable amount of data
    • Simultaneously view multiple waveform windows
  • Transaction viewing support for AXI memory mapped and AXI streaming interface
Source Code Debug

Vivado Simulator has a powerful source code debug environment that allows users to track and fix issues real time. The simulator allows users to control the debug environment through GUI and Tcl scripts.

Feature highlights:

  • Subprogram debug in GUI with Call-stack, Stack-frames and Local Objects windows
  • Step through simulation and make a detail evaluation of the RTL
  • Debug source code by adding breakpoints
  • View current values in text editor
  • Cross probe from schematic, RTL source and waveform
    • Single click simulation enables recompile and re-launch after HDL modification
C Co-Simulation

Vivado simulator enables the ability to have C and HDL interact using SystemVerilog based Direct Programming Interface (DPI) and Xilinx proprietary interface called XSI.  XSI is an optimal C interface for connecting C testbench to HDL since it enables Direct-C interface to simulation Kernel.

Feature highlights:

  • Swap slower RTL models with C models to improve simulation performance
  • Interface directly with simulation kernel
    • System Generator leverages XSI for co-simulation
  • Enable heterogeneous (VHDL, Verilog, C, Python…) simulation environment

Key Documents