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Write timing report to an RPX file

RPX files are binary files that enable you to create reports from a Tcl command and view the results in the graphical environment. The report commands that support this interface include: report_drc, report_methodology, report_power, report_timing, report_timing_summary, and report_utilization. To create the binary report, you can issue each of these Tcl commands with a –rpx <filename> option. When you open the design checkpoint in the graphical environment, you can access the report from by choosing File > Open Interactive Report. This mechanism is used by the project flow to restore all the reports when you open an implemented design.

Assign specific synthesis options to instances of your design

For the first time in Vivado v2017.1, RTL synthesis allows you to assign specific synthesis options to instances of your design. This is done through the new block_synth XDC property, it allows you to tune a design by optimizing differently various parts of your design: for example, a timing critical instance could be retimed while less timing critical instances could be optimized for area. No changes to the RTL or design setup are required, all can be done through XDC.

WaveformViewer in Vivado Simulator

Waveform viewer in Vivado simulator allows you to search for values. You can right click on the signal in waveform viewer and select find value or alternatively you can use Ctrl+Shift+F.

IP Encryption

Vivado now supports IP encryption based on IEEE 1735-2014 standard? Please watch this Quick Take Video to learn about IP encryption flow in Vivado and how to prepare IPs for encryption.

Automatic Generation of Simulation Scripts for Batch/Script Mode

The export_simulation command makes it a lot easier to run simulation in batch or script mode? This command collects all design files required for simulation and generates simulation script for the top-level RTL design or sub-design. The most important part is that it will generate script for all supported third-party simulator.

Accelerating Verification

Unified Simulation flow now allows running user Tcl scripts before compilation and after simulation step. Pre and post Tcl scripts give users better control of their simulation environment- for example, formatting .mem file or using custom scripts for managing signals in waveform viewer.

Debugging the code in Vivado simulator is even easier now with subprogram debug. Verilog and VHDL subprograms (task/functions) allow setting breakpoints and stepping through code.

Vivado HW Debug

Did you know that 2017.1 now provides transaction-level debugging for AXI interfaces in IP Integrator (IPI)?
Waveform window in Logic Analyzer now shows transactions for AXI interfaces read/write transfers. This feature makes AXI transaction-level debug at runtime easier than before! View this QTV to find out more!

Remote debugging capabilities expanded in 2017.1!
It is now possible to remotely debug your designs through PCIe interface without access to physical JTAG pins. This solution is especially useful for applications with limited access to the actual board such as data centers. This new solution provides all hardware and software pieces required for the host PC to interact with the design running in hardware. Look for the reference solution offered in the PCIe Gen3 IP example design! Find out more in PG156.

Need to debug your design that utilizes Partial Reconfiguration?
Vivado HW Debug now supports debug of designs utilizing Partial Reconfiguration! This support covers the debug within the static and/or any number of the reconfigurable portions of the design. In addition, it provides ease of use for bitfile management at runtime.

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