Overview

Xilinx's Verification IP (VIP) portfolio provides users with the ability to verify and debug their designs in a simulation environment easily, quickly, and more effectively. Verification IP cores are purpose built verification models whose goal is to ensure correct interoperability and system behavior. Companies in the EDA industry develop VIP for standards based interfaces (AXI, PCIe, SAS, SATA, USB, HDMI, ENET, etc..). Advantages to using VIP include improved design quality and reduced schedule time due to re-usability.

Xilinx's VIP cores are SystemVerilog based simulation models that provide full AXI protocol checking with ARM licensed assertions, support all major simulators, and are included in Vivado at no cost. Xilinx provides VIP for use in designs that use AXI component level (AXI-MM, AXI_Stream) and Processing System(Zynq®-7000) designs.

AXI Verification IP

  • Supports AXI3, AXI4 and AXI-Lite Protocols
  • Supports all protocol data widths and address widths, transfer types and responses
  • Full AXI Protocol Checker support
  • Integrated ARM Licensed Protocol Assertions
  • Transaction level protocol checking (burst type, length, size, lock type, cache type)
  • Configurable as Master, Slave or Passthrough modes of operation

AXI Stream Verification IP

  • Supports AXI4-Stream Protocol
  • Supports all protocol data widths and address widths, transfer types and responses
  • Full AXI Stream Protocol Checker support
  • Integrated ARM Licensed Protocol Assertions
  • Transaction level protocol checking (burst type, length, size, lock type, cache type)
  • Configurable as Master, Slave or Passthrough modes of operation

Zynq-7000 Verification IP

  • Allows for AXI transaction verification for programmable Logic to Processor System interfaces
  • Drop in replacement for Zynq-7000 BFM
  • Full AXI Protocol Checking
  • Supports AXI3 Protocol
  • Integrated ARM Licensed Protocol Assertions
  • Supports all 9 of the Zynq-7000 AXI interfaces
  • Task based API for transaction programming
  • 32/64–bit Data-width for AXI_HP, 32-bit for AXI_GP and 64-bit for AXI_ACP (Accelerator Cache Coherence Port)

MPSoC Verification IP

  • Supports AXI transaction verification between programmable Logic and Processor System in Zynq Ultrascale+ MPSoC
  • Supports 11 of AXI PL to PS data interfaces in  Zynq Ultrascale+ MPSoC
  • On-chip memory and DDR external memory models are included
  • Supports all AXI interfaces (AXI 4.0 complinat)
  • SystemVerilog task based API
  • Support for all Zynq UltraScale+ MPSoC supported burst lengths and burst sizes
  • Protocol checking provided with AXI VIP
Documentation

Documentation

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Training & Support
Video