Xilinx's Verification IP (VIP) portfolio provides users with the ability to verify and debug their designs in a simulation environment easily, quickly, and more effectively. Verification IP cores are purpose built verification models whose goal is to ensure correct interoperability and system behavior. Companies in the EDA industry develop VIP for standards based interfaces (AXI, PCIe, SAS, SATA, USB, HDMI, ENET, etc..). Advantages to using VIP include improved design quality and reduced schedule time due to re-usability.
Xilinx's VIP cores are SystemVerilog based simulation models that provide full AXI protocol checking with ARM licensed assertions, support all major simulators, and are included in Vivado at no cost. Xilinx provides VIP for use in designs that use AXI component level (AXI-MM, AXI_Stream) and Processing System(Zynq®-7000) designs.
Zynq Ultrascale+ MPSoC VIP – Provides functional simulation model of Zynq Ultrascale+ MPSoC based applications.
AXI Stream Verification IP – Provides full AXI Stream Protocol checking using ARM licensed assertions:
AXI Verification IP – Provides full AXI Protocol checking using ARM licensed assertions:
Zynq-7000 Verification IP - Provides simulation model of Zynq-7000 processing system