
Download Vivado™ ML Standard Edition free. Purchase licensing options for Enterprise Edition start at $2995.
Vivado ML Edition Features | Vivado ML Standard Edition | Vivado ML Enterprise Edition | Vivado Lab Edition |
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Licensing Option | Free | 30-day Evaluation - Free On Demand on AWS Marketplace NL: $2995 FL: $3595 |
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Device Support | Limited AMD Devices | All AMD Devices | |
Vivado IP Integrator | ![]() |
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Dynamic Function eXchange | ![]() |
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Vitis High-Level Synthesis | ![]() |
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Vivado Simulator | ![]() |
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Vivado Device Programmer | ![]() |
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Vivado Logic Analyzer | ![]() |
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Vivado Serial I/O Analyzer | ![]() |
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Debug IP (ILA/VIO/IBERT) | ![]() |
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Synthesis and Place and Route | ![]() |
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Vitis Model Composer | Buy NL - $500 FL - $700 |
Buy NL - $500 FL - $700 |
The following tables provide the typical and peak Vivado memory usage per target device. AMD recommends to have have at minimum enough physical system memory to handle the peak memory usage.
Notes:
Versal AI Edge Series | Windows / Linux (64-bit) | |
Minimum | Recommended | |
All Devices* | 32 | 64 |
*Note: End-to-end flow targeting any AIE/AIE-ML device would be using Vitis. Use Vitis memory recommendations (UG1400) for those devices which include Vivado implementation tools.
Versal AI Core Series | Windows / Linux (64-bit) | |
Minimum | Recommended | |
All Devices* | 32 | 64 |
*Note: End-to-end flow targeting any AIE/AIE-ML device would be using Vitis. Use Vitis memory recommendations (UG1400) for those devices which include Vivado implementation tools.
Versal Prime Series | Windows / Linux (64-bit) | |
Device | Typical | Peak |
XCVM1102 | 6 | 12 |
XCVM1302 | 9 | 16 |
XCVM1402 | 12 | 20 |
XCVM1502 | 10 | 17 |
XCVM1802 | 17 | 28 |
XCVM2202 | 11 | 18 |
XCVM2302 | 15 | 24 |
XCVM2502 | 17 | 28 |
XCVM2902 | 18 | 29 |
Versal HBM Series | Windows / Linux (64-bit) | |
Device | Typical | Peak |
XCVH1522 | 33 | 56 |
XCVH1542 | 33 | 56 |
XCVH1582 | 33 | 56 |
XCVH1742 | 40 | 60 |
XCVH1782 | 40 | 60 |
Kintex UltraScale+ | Windows / Linux (64-bit) | |
Device | Typical | Peak |
XCKU3P | 7 | 13 |
XCKU5P | 7 | 13 |
XCKU9P | 8 | 13 |
XCKU11P | 9 | 13 |
XCKU13P | 10 | 14 |
XCKU15P | 10 | 15 |
XCVU19P | 16 | 24 |
Virtex UltraScale+ | Windows / Linux (64-bit) | |
Device | Typical | Peak |
XCVU3P | 11 | 19 |
XCVU5P | 12 | 19 |
XCVU7P | 15 | 24 |
XCVU9P | 20 | 32 |
XCVU11P | 22 | 32 |
XCVU13P | 28 | 47 |
XCVU19P | 48 | 64 |
XCVU23P | 20 | 32 |
XCVU27P | 22 | 32 |
XCVU29P | 28 | 47 |
XCVU31P | 14 | 22 |
XCVU33P | 14 | 22 |
XCVU35P | 17 | 28 |
XCVU37P | 25 | 37 |
XCVU45P | 17 | 28 |
XCVU47P | 25 | 37 |
XCVU57P | 25 | 37 |
Zynq UltraScale+ | Windows / Linux (64-bit) | |
Device | Typical | Peak |
XCZU2EG | 3 | 5 |
XCZU3EG | 4 | 6 |
XCZU4EV | 5 | 8 |
XCZU5EV | 6 | 9 |
XCZU6EG | 7 | 10 |
XCZU7EV | 8 | 11 |
XCZU9EG | 10 | 14 |
XCZU11EG | 11 | 18 |
XCZU15EG | 11 | 18 |
XCZU17EG | 12 | 18 |
XCZU19EG | 14 | 21 |
Zynq UltraScale+ RFSoC | Windows / Linux (64-bit) | |
Device | Typical | Peak |
XCZU21DR | 10 | 14 |
XCZU25DR | 11 | 14 |
XCZU27DR | 13 | 17 |
XCZU28DR | 14 | 17 |
XCZU29DR | 14 | 17 |
Kintex UltraScale | Windows / Linux (64-bit) | |
Device | Typical | Peak |
XCKU025 | 5 | 7 |
XCKU035 | 5 | 7 |
XCKU040 | 5 | 7 |
XCKU060 | 7 | 11 |
XCKU085 | 9 | 14 |
XCKU095 | 9 | 14 |
XCKU115 | 9 | 14 |
Virtex UltraScale | Windows / Linux (64-bit) | |
Device | Typical | Peak |
XCVU065 | 7 | 11 |
XCVU080 | 8 | 12 |
XCVU095 | 9 | 14 |
XCVU125 | 10 | 16 |
XCVU160 | 14 | 20 |
XCVU190 | 18 | 24 |
XCVU440 | 32 | 48 |
Virtex 7 | Windows / Linux (64-bit) | |
Device | Typical | Peak |
XC7V585T | 4 | 6 |
XC7V2000T | 10 | 16 |
XC7VX330T | 3 | 5 |
XC7VX415T | 3 | 5 |
XC7VX485T | 4 | 5 |
XC7VX550T | 4 | 6 |
XC7VX690T | 5 | 7 |
XC7VX980T | 7 | 9 |
XC7VX1140T | 8 | 10 |
XC7VH580T | 4 | 6 |
XC7VH870T | 6 | 8 |
Virtex 7 | Windows / Linux (64-bit) | |
Device | Typical | Peak |
XC7K70T | 1.6 | 2.5 |
XC7K160T | 2 | 3 |
XC7K325T | 3 | 4 |
XC7K355T | 3 | 5 |
XC7K410T | 3 | 5 |
XC7K420T | 3 | 5 |
XC7K480T | 4 | 6.5 |
Artix 7 | Windows / Linux (64-bit) | |
Device | Typical | Peak |
XC7A15T | 2 | 3 |
XC7A35T | 2 | 3 |
XC7A50T | 2 | 3 |
XC7A75T | 2 | 3 |
XC7A100T | 2 | 3 |
XC7A200T | 2.5 | 3.5 |
Zynq 7000 | Windows / Linux (64-bit) | |
Device | Typical | Peak |
XC7Z010 | 1 | 1.6 |
XC7Z015 | 1.3 | 1.9 |
XC7Z020 | 1.3 | 1.9 |
XC7Z030 | 1.8 | 2.7 |
XC7Z035 | 3 | 5 |
XC7Z045 | 3 | 5 |
AMD supports the following operating systems on x86 and x86-64 processor architectures.
Note: Please refer to PetaLinux Tools Documentation: Reference Guide (UG1144) for more information on Installation Requirements for supported Operating Systems with PetaLinux.
The following table lists architecture support for commercial products in Vivado ML Standard versus Vivado ML Enterprise edition. For non-commercial support, all AMD automotive devices are supported in Vivado ML Standard Edition when available as production devices in the tools.
Architecture | Vivado ML Standard Edition | Vivado ML Enterprise Edition |
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Zynq™ 7000 SoC | • XC7Z007S, XC7Z010, XC7Z012S, XC7Z014S, XC7Z015, XC7Z020, and XC7Z030 | • All devices |
Zynq UltraScale+™ MPSoC |
• XCZU1EG, XCZU1CG, XCZU2EG, XCZU2CG, XCZU3EG, XCZU3CG XCZU4EG, XCZU4CG, XCZU4EV, XCZU5EG, XCZU5CG, XCZU5EV, XCZU7EV, XCZU7EG, and XCZU7CG | • All devices |
Zynq UltraScale+ RFSoC | • None | • All devices |
Alveo™ Data Center Accelerator Card | • All devices | • All devices |
Kria™ SOM | • All devices | • All devices |
Versal™ Adaptive SoC | • None | Versal AI Core Series: Versal Prime Series: |
Virtex™ FPGA | Virtex 7 FPGA: Virtex UltraScale FPGA: |
Virtex 7 FPGA: Virtex UltraScale FPGA: Virtex UltraScale+ FPGA: Virtex UltraScale+ HBM FPGA: Virtex UltraScale+ 58G PAM4 FPGA: |
Kintex™ FPGA | Kintex 7 FPGA: Kintex UltraScale FPGA: Kintex UltraScale+ FPGA: |
Kintex 7 FPGA: Kintex UltraScale FPGA: Kintex UltraScale+ FPGA: |
Artix™ FPGA | Artix 7 FPGA: • All devices Artix UltraScale+ FPGA: • All devices |
Artix 7 FPGA: Artix UltraScale+ FPGA: |
Spartan™ 7 FPGA | • All devices |
• All devices |
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Access the below free Vivado ML training courses when you sign up for the Developer Program.
Video Title | Description |
---|---|
Introduction to FPGAs | Provides an overview of FPGA architecture and describes the advantages, applications, and major building blocks of FPGAs. |
FPGA & Adaptive SoC Families | Introduces 7 series and UltraScale™ FPGAs, stacked silicon interconnect-based 3D IC devices, Zynq™ 7000 SoCs, Zynq UltraScale+™ MPSoCs, and Adaptive Compute Acceleration Platforms (ACAPs). |
Introduction to the Vivado Design Suite | Describes various design flows and the role of the Vivado IDE in the flows. |
Vivado Design Suite Project-based Mode | Introduces the project-based flow in the Vivado Design Suite: creating a project, adding files to the project, exploring the Vivado IDE, and simulating the design. |
Vivado Design Suite Non-Project Based Mode | Describes the design flow using non-project batch mode, including using design analysis commands and how constraints are managed in non-project mode. |
UltraFast Design Methodology: Board and Device Planning | Introduces the methodology guidelines covered in this course and the UltraFast Design Methodology checklist. |
RTL Development | Covers RTL and the RTL design flow, recommended coding guidelines, using control signals, and recommendations on resets. |
Behavioral Simulation | Describes the process of behavioral simulation and the simulation options available in the Vivado IDE. |
Vivado Synthesis, Implementation, and Bitstream Generation | Reviews creating timing constraints according to the design scenario, synthesizing and implementing the design, and, optionally, generating and downloading a bitstream to a demo board. |
Vivado Design Suite I/O Pin Planning | Use the I/O Pin Planning layout to perform pin assignments in a design. |
Vivado IP Flow | Customize IP, instantiate IP, and verify the hierarchy of your design IP. |
Looking for additional on-demand training courses? When you join the developer program, you also receive a 50% discount on select courses!
1. Log into https://lmstraining.xilinx.com with your AMD developer account
2. Search Developers Program in the search box to populate the discounted courses
3. Purchase and get started
Video Title | Description |
---|---|
Designing FPGAs Using the Vivado Design Suite 1 | This training content offers introductory training on the Vivado™ Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design. |
Designing FPGAs Using the Vivado Design Suite 2 | This content builds on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course. Learn how to build a more effective FPGA design. |
Designing FPGAs Using the Vivado Design Suite 3 | This content builds further on the previous Designing FPGAs Using the Vivado Design Suite 1 & 2.Learn how to effectively employ timing closure techniques. |
Designing FPGAs Using the Vivado Design Suite 4 | Learn how to use the advanced aspects of the Vivado Design Suite and AMD hardware. The focus is on applying timing constraints for source-synchronous and system-synchronous interfaces, utilizing floorplanning techniques, and more. |
AMD hands-on FPGA and Embedded Design training provides you the foundational knowledge necessary to begin designing right away. These programs target both engineers new to FPGA technology and experienced engineers developing complex connectivity, digital signal processing, or embedded solutions. Contact your local Sales Rep or Authorized Training Provider to see if your company has any Training Credits available. Learn more