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MIPI I3C Master Controller IP

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Product Description

The MIPI I3C interface is an evolutionary standard that improves upon the features of I2C, while maintaining backward compatibility. This standard offers a flexible multi-drop interface between the host processor and peripheral sensors to support the growing usage of sensors in embedded systems.

Key Features and Benefits

  • Compliant with MIPI I3C Specification V1.0
  • Compliant with MIPI I3C HCI Specification V1.0
  • Supports up to 12.5 MHz operation using Push-Pull
  • Open-Drain and Push-pull type transactions (as required)
  • Supports legacy I2C devices
  • Dynamic Addressing while supporting Static Addressing for Legacy I2C devices
  • Legacy I2C Messaging
  • I2C-like Single Data Rate Messaging (SDR)
  • Optional High Data Rate Messaging Modes (HDR)
  • Support for Multi-master (transferring the ownership of the bus to a Secondary Master if Present)
  • Reception of In-band Interrupt Support from the I3C Slave devices
  • Reception of Hot-Join from newly added I3C Slave devices
  • Synchronous Timing Support and Asynchronous Time Stamping.
  • APB/AHB Target Interface for Configuring/Controlling the IP with Interrupt output
  • Small 16-byte (Configurable) FIFO for transferring data between Master and the Slave devices
  • Independent Clocks for AHB and the I3C Interface

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU17EG -2 Vivado 2020.1 7706 4622 0 0 0 0 12

IP Quality Metrics

General Information

This Data was Current On Dec 09, 2020
Current IP Revision Number 1.1
Date Current Revision was Released Oct 04, 2018
Release Date of First Version Nov 28, 2017

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 5
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Source Code
Source Code Format(s) Verilog
High-Level Model Included? N
Model Formats Other
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog
Code Coverage Report Provided? Y
Functional Coverage Report Provided? N
UCFs Provided? XDC
Commercial Evaluation Board Available? Y
FPGA Used on Board Kintex-7
Software Drivers Provided? Y
Driver OS Support Y

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis / 2018.2
Static Timing Analysis Performed? N
AXI Interfaces AXI4-Lite
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Both
Assertions N
Coverage Metrics Collected Code
Timing Verification Performed? N
Timing Verification Report Available Y
Simulators Supported Cadence NC-Sim / 15.2

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used KC705
Industry Standard Compliance Testing Passed N
Are Test Results Available? N