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ACE-NIC100

Product Description

ACE-NIC100 offers flexible 10/25/40/100G Ethernet connectivity and a programmable FPGA acceleration Flow Processor in a single standard adapter card, providing best-in-class NFV and security acceleration for CSPs, enterprise data centers, and standalone solutions.


Key Features and Benefits

  • IPSec high-speed tunnel offload
  • Supports dedicated queues in hardware to shape and schedule traffic based on priority
  • Hierarchical Quality of Service (QoS) supporting 32K queues
  • IP packet fragmentation
  • Jumbo frame support
  • DPDK offload and acceleration
  • OAM/BFD
  • 4K virtual interfaces
  • 1M filter rules
  • Protocol interworking: L2/L3/MPLS/Overlay/NAT
  • Сonnecting high speed networks: 10/25/40/100G interfaces
  • Ideal for telco and enterprise solutions with performance-hungry applications

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Kintex-UP Family XCKU15P -2 Vivado 2018.2 Y 60647 305607 863 1750 5 24 250

IP Quality Metrics

General Information

This Data was Current On Apr 15, 2019
Current IP Revision Number 2.1.5
Date Current Revision was Released Mar 21, 2019
Release Date of First Version Sep 27, 2018

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 3
Can References be Made Available? N

Deliverables

IP Formats Available for Purchase Bitstream
Source Code Format(s) Verilog,
High-Level Model Included? N
Model Formats C++
Integration Testbench Provided Y
Integration Test Bench Format(s) C/C++
Code Coverage Report Provided? N
Functional Coverage Report Provided? Y
UCFs Provided? N
Commercial Evaluation Board Available? Y
FPGA Used on Board Kintex UltraScale+
Software Drivers Provided? Y
Driver OS Support All

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Instantiation
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Synplicity Synplify
Static Timing Analysis Performed? Y
AXI Interfaces AXI4
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Both
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor Questa

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ACE-NIC100 board
Industry Standard Compliance Testing Passed N
Are Test Results Available? N
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