True Random Number Generator
- Part Number: XIP8001B
- Vendor: Xiphera Ltd
- Partner Tier: Elite Certified
Product Description
XIP8001B from Xiphera is a True Random Number Generator (TRNG) Intellectual Property (IP) core, which has been designed for easy integration with other FPGA functionality, as the functionality of XIP8001B does not rely on any FPGA-specific features.
XIP8001B includes the NIST SP 800-90B specified startup tests and online health tests. XIP8001B has been successfully tested with PractRand, gjrand, TestU01, the NIST SP 800-22 statistical test suite and the dieharder test suite. XIP8001B includes a NIST SP 800-90B compliant AES-CBC-MAC -based entropy extractor, thus making XIP8001B suitable for use in a crypto module targeting a FIPS 140-3 certification. certification.On request, the core is shipped with a Linux driver for easy integration with software.
Key Features and Benefits
- Compact Size
- Autonomous Operation
- Parameterizability
- Standard Compliance
- Passes Statistical Tests
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Kintex-UP Family | XCKU3P | -2 | Vivado 2020.2 | 0 | 1468 | 1 | 0 | 0 | 0 | 354 | |
| Zynq-UP-MPSoC Family | XCZU3CG | -1 | Vivado 2020.2 | Y | 0 | 1461 | 1 | 0 | 0 | 0 | 331 |
| Spartan-7 Family | XC7S25 | -2 | Vivado 2020.2 | 438 | 1475 | 1 | 0 | 0 | 0 | 212 | |
| Zynq-7000 Family | XC7Z020 | -1 | Vivado 2020.2 | Y | 454 | 1481 | 1 | 0 | 0 | 0 | 167 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 23, 2023 |
| Current IP Revision Number | 1.3 |
| Date Current Revision was Released | Feb 10, 2021 |
| Release Date of First Version | Nov 21, 2019 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 4 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Netlist, Source Code |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | VHDL |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | N |
| Commercial Evaluation Board Available? | N |
| FPGA Used on Board | N/A |
| Software Drivers Provided? | N |
| Driver OS Support | Linux |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Vivado Synthesis / 2020.2 |
| Static Timing Analysis Performed? | N |
| AXI Interfaces | , AXI4-Lite |
| IP-XACT Metadata Included? | Y |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | None |
| Assertions | N |
| Coverage Metrics Collected | None |
| Timing Verification Performed? | N |
| Timing Verification Report Available | N |
| Simulators Supported | Xilinx lSim / 19.1 |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | ZedBoard |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |