Non-Uniform Correction (NUC)-IP Core

Product Description

The Non-Uniform Correction IP core is designed to work with a thermal camera to process thermal raw image data and to filter out the fixed pattern noise (FPN) along with adjustment of contrast, brightness and gain. The IP consists of an AXI4-Lite interface which allows easy IP control.


Key Features and Benefits

  • Can process raw thermal streams
  • Implement filtering functionality as FPN
  • Configurable parameter resolution, contract, gain mode etc
  • Supports AXI4 interface for configuring and processing thermal streams
  • Supports resolution upto 1080p
  • Supports 16 or 14 bit input and generate 16bit monochrome output

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K325T -2 Vivado 2019.2 3754 10767 15 17 0 0 200

IP Quality Metrics

General Information

This Data was Current On Aug 16, 2021
Current IP Revision Number v1.0
Date Current Revision was Released Aug 13, 2021
Release Date of First Version Aug 10, 2021

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 2
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Source Code, Netlist
Source Code Format(s) Verilog
High-Level Model Included? Y
Model Formats C++
Integration Testbench Provided N
Code Coverage Report Provided? Y
Functional Coverage Report Provided? N
UCFs Provided? N
Commercial Evaluation Board Available? Y
FPGA Used on Board Kintex-7
Software Drivers Provided? N
Driver OS Support Yes

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques UltraFast Design Methodology, Other Optimization Techniques
Custom FPGA Optimization Techniques HLS Optimization Methodology
Synthesis Software Tools Supported/Version Vivado Synthesis / 2019.2
Static Timing Analysis Performed? N
AXI Interfaces AXI4-Lite, AXI4-Stream, AXI4
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology None
Assertions N
Coverage Metrics Collected Code
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Xilinx lSim / 2019.2

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used VIVADO 2019.2
Industry Standard Compliance Testing Passed N
Are Test Results Available? N