SIMD-512 Hash Core

Product Description

SIMD is a cryptographic hash function based on the Merkle–Damgard construction submitted to the NIST hash function competition as a sha-3 candidate. It is one of fourteen entries to be accepted into round two of the competition. The most important component of SIMD is its message expansion, which is designed to give a high minimum distance.

Key Features and Benefits

  • Very high throughput of 35.7 GBps with fully pipelined architecture with the initiation interval of 1
  • Optimized to run at high frequency of 600Mhz in Xilinx VU9P and Xilinx VU13P FPGA Devices
  • Both input and output width are 512 bits
  • Latency of the Core is 112 cycles or 186.6 ns

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU13P -2 Vivado 2020.2 0 171137 0 512 0 0 600

IP Quality Metrics

General Information

This Data was Current On Sep 01, 2021
Current IP Revision Number V2.0
Date Current Revision was Released Jan 07, 2020
Release Date of First Version Feb 01, 2019

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 1
Can References be Made Available? N


IP Formats Available for Purchase Source Code
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? N
Commercial Evaluation Board Available? N
FPGA Used on Board Virtex UltraScale+
Software Drivers Provided? N


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Other Optimization Techniques
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis / 2020.2
Static Timing Analysis Performed? N
IP-XACT Metadata Included? N


Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Code
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Xilinx lSim / 2020.2

Hardware Validation

Validated on FPGA N
Industry Standard Compliance Testing Passed N
Are Test Results Available? N