Product Description

Hamsi is a family of cryptographic hash functions. It is based on the Concatenate-Permute-Truncate design strategy used in several hash functions like Snefru and Grindhal.It uses a message expansion and a feedforward of the chaining value in each round. The non-linear permutation required for the design uses the linear transformation and one of the Sbox of the block cipher Serpent .

Key Features and Benefits

  • Very high throughput of 35.7 GBps with fully pipelined architecture
  • Optimized to run at high frequency of 600Mhz in VU9P and VU13P FPGA Devices
  • The input and output width are 512 bits.
  • Latency of the Core is 89 cycles or 148.3 ns

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU13P -2 Vivado 2020.2 0 180230 0 0 0 0 600

IP Quality Metrics

General Information

This Data was Current On Sep 01, 2021
Current IP Revision Number V2
Date Current Revision was Released Dec 15, 2020
Release Date of First Version Feb 28, 2019

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 0
Can References be Made Available? N


IP Formats Available for Purchase Source Code
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? Y
Functional Coverage Report Provided? Y
UCFs Provided? N
Commercial Evaluation Board Available? N
FPGA Used on Board N/A
Software Drivers Provided? N


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Other Optimization Techniques
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis / 2020.2; Vivado Synthesis / 2018.1
Static Timing Analysis Performed? N
IP-XACT Metadata Included? N


Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Code
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Xilinx lSim / 2018.1; Xilinx lSim / 2020.2

Hardware Validation

Validated on FPGA N
Industry Standard Compliance Testing Passed N
Are Test Results Available? N