Auto Contrast Enhancement (ACE) IP Core

Product Description

The Auto Contrast Enhancement (ACE) IP core produces the low-contrast enhanced output stream by histogram analysis of the input stream without loss of image details. The IP follows AXI4 protocol allowing easy IP integration with the user’s design. IP core has AXI4 interface ports for stream, memory and control.


Key Features and Benefits

  • Generates contrast-enhanced output
  • Configurable parameters such as resolution, gray level, enhance mode( 0 - original unenhanced output, 1 - contrast-enhanced output)
  • Supports a maximum of 1920x1080, resolution with 1 pixel per clock
  • Supports 24-bit RGB input and output
  • AXI4-Lite control interface
  • AXI4-Stream interface for input and output video
  • AXI4-MM interface for reading stream data from memory

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K325T -2 Vivado 2019.2 4109 11328 10 40 0 0 200

IP Quality Metrics

General Information

This Data was Current On Sep 01, 2021
Current IP Revision Number v1.0
Date Current Revision was Released Aug 27, 2021
Release Date of First Version Aug 27, 2021

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 1
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Source Code, Netlist
Source Code Format(s) VHDL, Verilog
High-Level Model Included? Y
Model Formats C++
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? Y
UCFs Provided? N
Commercial Evaluation Board Available? Y
FPGA Used on Board Artix-7
Software Drivers Provided? N

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques UltraFast Design Methodology
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST / 2019.2; Vivado Synthesis / 2019.2 ,2018.1 and 2018.2
Static Timing Analysis Performed? N
AXI Interfaces AXI4-Lite, AXI4-Stream, AXI4
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Code
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Xilinx lSim / 2019.2

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used KC705, AC701 and Nexys 4 DDR
Industry Standard Compliance Testing Passed N
Are Test Results Available? N