13 Different Cryptographic Hash Functions Core

Product Description

These are 13 different cryptographic hash function originally submitted to NIST hash function competition which made upto round 2. All of these cores are designed to deliver extremely high throughput of 35.7GBps with fully pipelined architecture running at 600Mhz on Ultrascale+ FPGAs. In this bundle of cores we have SHA-3, Keccak, Blake, Grostl, JH, Skein Cores that got selected for NIST round 3 and BMW, Echo, Shabal, Cubehash, Fugue and Luffa from NIST round 2. We also have Whirlpool hash function on this bundle. It is primarily targeted for extremely high throughput applications with input and output width of 512-bit while the Core can be modified for any bit-width and range of applications like Security, FinTech and Encryption/Decryption.

Key Features and Benefits

  • Throughput of 35.7GBps
  • Initiation interval of 1
  • Maximum clock frequency of 600MHz
  • LUT Consumption ranging from 47280 to 330960

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU13P -2 Vivado 2018.2 0 48500 0 0 0 0 600

IP Quality Metrics

General Information

This Data was Current On Sep 15, 2021
Current IP Revision Number v1.0
Date Current Revision was Released Aug 30, 2019
Release Date of First Version Aug 30, 2019

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 0
Can References be Made Available? N


IP Formats Available for Purchase Source Code
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog, VHDL
Code Coverage Report Provided? Y
Functional Coverage Report Provided? N
UCFs Provided? N
Commercial Evaluation Board Available? N
FPGA Used on Board N/A
Software Drivers Provided? N


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Other Optimization Techniques
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis / 2018.2
Static Timing Analysis Performed? N
IP-XACT Metadata Included? N


Is a Document Verification Plan Available? Yes, document only plan
Test Methodology None
Assertions N
Coverage Metrics Collected Code
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Xilinx lSim / 2018.2

Hardware Validation

Validated on FPGA N
Industry Standard Compliance Testing Passed N
Are Test Results Available? N