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H.264 Encoder - Micro Footprint
The A2e H.264 Encoder is still the industry’s smallest and fastest, which makes it ideal for FPGA designs with limited resources. A single core is capable of compressing 1080p30 video in a Spartan 6 device. The A2e H.264 Encoder supports H.264 variable and fixed bit-rate encoding of video streams. Multiple cores can be used for processing larger size or higher bandwidth images. We’ve added several enhancements to the latest revision of the core and supporting
Key Features and Benefits
Highly optimized Xilinx FPGA Footprint
Supports resolutions up to 4096 x 4096 (multiple instantiations)
Variable Bit Rate (VBR) and Constant Bit Rate (CBR)
Verilog Source and Netlist versions available
Pre-packaged for Coregen via IP-XACT
Entropy Encoding: CAVLC
Fully compatible with the ITU-T H.264 specification
Fully synchronous design
Generates I and P frames
Profile level 3.1 is supported
Search range: 80 x 48 pixels, Full, ½, ¼ pixel resolution
Support for Single or Multiple slices via firmware control
Support for intra 4 x 4 DC prediction
Supports YUV 4:2:0 video input
Supports simultaneous encoding of multiple streams of arbitrary sizes and compression ratios
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
Spartan 6 Family
IP Quality Metrics
This Data was Current On
Oct 25, 2019
Current IP Revision Number
Date Current Revision was Released
Feb 01, 2016
Release Date of First Version
Aug 24, 2011
Production Use by Xilinx Customers
Number of Successful Xilinx Customer Production Projects
Can References be Made Available?
IP Formats Available for Purchase
Netlist, Source Code
Source Code Format(s)
High-Level Model Included?
Integration Testbench Provided
Integration Test Bench Format(s)
Code Coverage Report Provided?
Functional Coverage Report Provided?
Commercial Evaluation Board Available?
Software Drivers Provided?
Driver OS Support
Code Optimized for Xilinx?
Custom FPGA Optimization Techniques
Synthesis Software Tools Supported/Version
Xilinx XST / 12.3
Static Timing Analysis Performed?
IP-XACT Metadata Included?
Is a Document Verification Plan Available?
Executable and documented plan
Coverage Metrics Collected
Timing Verification Performed?
Timing Verification Report Available
Mentor ModelSIM / 6.5d
Validated on FPGA
Hardware Validation Platform Used
Xilinx ZC-702 with Avnet FMC
Industry Standard Compliance Testing Passed
Specific Compliance Test
Are Test Results Available?