Product Description
The A2e H.264 Encoder is still the industry’s smallest and fastest, which makes it ideal for FPGA designs with limited resources. A single core is capable of compressing 1080p30 video in a Spartan 6 device. The A2e H.264 Encoder supports H.264 variable and fixed bit-rate encoding of video streams. Multiple cores can be used for processing larger size or higher bandwidth images. We’ve added several enhancements to the latest revision of the core and supporting material.
Key Features and Benefits
- Highly optimized Xilinx FPGA Footprint
- Supports resolutions up to 4096 x 4096 (multiple instantiations)
- Variable Bit Rate (VBR) and Constant Bit Rate (CBR)
- Verilog Source and Netlist versions available
- Pre-packaged for Coregen via IP-XACT
- Entropy Encoding: CAVLC
- Fully compatible with the ITU-T H.264 specification
- Fully synchronous design
- Generates I and P frames
- Profile level 3.1 is supported
- Search range: 80 x 48 pixels, Full, ½, ¼ pixel resolution
- Support for Single or Multiple slices via firmware control
- Support for intra 4 x 4 DC prediction
- Supports YUV 4:2:0 video input
- Supports simultaneous encoding of multiple streams of arbitrary sizes and compression ratios
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| KINTEX-7 Family | XC7K160T | -3 | Vivado 2015.4 | N | 3939 | 10226 | 9 | 8 | 0 | 0 | 200 |
| Zynq-7000 Family | XC7Z020 | -1 | Vivado 2015.4 | Y | 4670 | 11300 | 9 | 8 | 0 | 0 | 131 |
| Spartan 6 Family | XC6SLX150 | -3 | Vivado 2015.4 | Y | 3945 | 10505 | 22 | 8 | 0 | 0 | 87 |
| VIRTEX6LXT Family | XC6VLX130T | -2 | Vivado 2015.4 | Y | 3936 | 9804 | 9 | 8 | 0 | 0 | 142 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 25, 2019 |
| Current IP Revision Number | 2.02030 |
| Date Current Revision was Released | Feb 01, 2016 |
| Release Date of First Version | Aug 24, 2011 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 30 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Netlist, Source Code |
| Source Code Format(s) | Verilog |
| High-Level Model Included? | Y |
| Model Formats | C |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | Verilog |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | UCF |
| Commercial Evaluation Board Available? | Y |
| Software Drivers Provided? | Y |
| Driver OS Support | NA |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Xilinx XST / 12.3 |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4, AXI4-Lite |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Executable and documented plan |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Mentor ModelSIM / 6.5d |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | Xilinx ZC-702 with Avnet FMC |
| Industry Standard Compliance Testing Passed | N |
| Specific Compliance Test | NA |
| Are Test Results Available? | N |