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  3. Automatic Gain Control(AGC) IP Core

Automatic Gain Control(AGC) IP Core

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Product Description

The Automatic Gain Control IP core takes in camera images via the AXI4-Stream source and then automatically calculates the alpha and beta values for the input image and sets the output of the input image using the calculated alpha and beta values.

Key Features and Benefits

  • Calculates alpha and beta values automatically.
  • Provides the gain corrected output image.
  • Configurable parameters such as resolution.
  • Supports 24-bit RGB input and output.
  • AXI4 compatible IP core, easy to integrate on Computer Vision IP Pipeline or Camera Pipeline on VIVADO or Vitis.

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-7000 Family XC7Z045 -2 Vivado 2019.1 Y 2821 7440 5 31 0 0 150

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number V1.0
Date Current Revision was Released May 05, 2022
Release Date of First Version May 05, 2022

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 0
Can References be Made Available? N

Deliverables

IP Formats Available for Purchase Source Code
Source Code Format(s) Verilog, VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? Y
Functional Coverage Report Provided? N
UCFs Provided? N
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq-7000
Software Drivers Provided? N

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis / 2019.1
Static Timing Analysis Performed? N
AXI Interfaces AXI4, AXI4-Stream, AXI4-Lite
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Code
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Xilinx lSim / 2019.1

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ZC706
Industry Standard Compliance Testing Passed N
Are Test Results Available? N