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logi3D Scalable 3D Graphic Accelerator

Product Description

The logi3D Scalable 3D Graphics Accelerator IP core is the Graphics Processing Unit (GPU) specifically designed for the Xilinx Zynq-7000 SoC. The logi3D enables designers to add attractive 2D and 3D graphics, including advanced Graphical User Interfaces (GUI), to their Xilinx Zynq-7000 SoC. This high performing 3D GPU can be implemented with other soft IP cores in Zynq-7000 SoC programmable logic and interfaced with an industry-standard ARM dual-core Cortex-A9 MPCore processing system available on the same chip. Due to its AMBA AXI4 compliance the logi3D IP core can also be implemented in Xilinx 7 Series and other Xilinx FPGA families as a graphics coprocessor in various ASSP plus FPGA combinations. The logi3D Scalable 3D Graphics Accelerator IP core is designed to support the OpenGL ES 1.1 API*. Xylon provides software support for Linux, Android and Microsoft Windows Embedded Compact operating systems.

* Product is based on published Khronos Specification, and is expected to pass the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.

Key Features and Benefits

  • The logi3D GPU can be used with different CPUs
  • ARM Cortex-A9 CPU with NEON coprocessor run the geometry engine and optimizes the IP's size
  • Programmable logic resource-effective 3D graphics acceleration
  • Linux, Android and Windows Embedded Compact compatible
  • Conformant to the AMBA AXI4 bus specifications from ARM
  • Graphics accelerator IP designed to support the OpenGL ES 1.1 API (Common Profile)
  • Supports Safety Critical OpenGL SC 1.0.1

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-7000 Family XC7Z020 -1 Vivado 2018.3 Y 7706 25540 14 38 0 0 170

IP Quality Metrics

General Information

This Data was Current On Apr 15, 2019
Current IP Revision Number 1.6.1
Date Current Revision was Released Apr 12, 2019
Release Date of First Version Jan 01, 2007

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 11
Can References be Made Available? N


IP Formats Available for Purchase Netlist, Source Code, Bitstream
Source Code Format(s) VHDL
High-Level Model Included? Y
Model Formats C++
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Spartan-6
Software Drivers Provided? Y
Driver OS Support Linux, WEC, Android


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference, Instantiation
Custom FPGA Optimization Techniques The IP targeted to Xilinx EPP and FPGA.
Synthesis Software Tools Supported/Version Xilinx XST / 13.2
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Lite, AXI4
IP-XACT Metadata Included? N


Is a Document Verification Plan Available? No
Test Methodology Directed Testing
Assertions Y
Coverage Metrics Collected None
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor ModelSIM / 6.4c

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ZC702, ZC706, ZedBoard
Industry Standard Compliance Testing Passed N
Are Test Results Available? N
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