2. Intellectual Property
  3. logi3D Scalable 3D Graphic Accelerator

logi3D Scalable 3D Graphic Accelerator

  • Part Number: logi3D
  • Vendor: Xylon d.o.o.
  • Premier Alliance Member
Request Information
Evaluate IP

Product Description

The logi3D IP core is specifically designed for the Xilinx Versal Adaptive Compute Acceleration Platform (ACAP) and Xilinx Zynq-7000 SoC family. SoC designers can add attractive 3D graphics, including advanced Graphical User Interfaces (GUI), to their Xilinx ACAP/SoC design by combining the logi3D with their application specific IP cores in a plug-and-play manner. The IP core is designed to support the OpenGL ES 1.1. API. Currently supported operating system is Linux. Due to its AMBA AXI4 interface compliance the logi3D IP core can also be implemented on Xilinx 7 Series and other Xilinx FPGA families as a Graphics Processing Unit (GPU) in various ASSP plus FPGA combinations. The logi3D IP core has a small footprint and enables efficient implementation in the smallest Versal ACAP device. It enables system designers to fully exploit heterogeneous computing and networking resources available on Xilinx's unique Adaptive Compute Acceleration Platform, and to round their design with graphics capability.

* Product is based on published Khronos Specification, and is expected to pass the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.

Key Features and Benefits

  • The logi3D GPU can be used with different CPUs
  • ARM processing system (1 core) runs the geometry engine and optimizes the IP's size
  • Programmable logic resource-effective 3D graphics acceleration
  • Linux OS compatible
  • Conformant to the AMBA AXI4 bus specifications from ARM
  • Graphics accelerator IP designed to support the OpenGL ES 1.1 API (Common Profile)
  • Supports Safety Critical OpenGL SC 1.0.1

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VERSAL_AI_CORE Family XCVC1902 -1 Vivado 2020.2 Y 0 49143 46 21 0 0 180
Zynq-7000 Family XC7Z020 -1 Vivado 2018.3 Y 7706 25540 14 38 0 0 170

IP Quality Metrics

General Information

This Data was Current On Mar 05, 2021
Current IP Revision Number 3.0
Date Current Revision was Released Feb 26, 2021
Release Date of First Version Jan 01, 2007

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 15
Can References be Made Available? N

Deliverables

IP Formats Available for Purchase Netlist, Source Code, Bitstream
Source Code Format(s) VHDL
High-Level Model Included? Y
Model Formats C++
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Spartan-6
Software Drivers Provided? Y
Driver OS Support Linux, WEC, Android

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference, Instantiation
Custom FPGA Optimization Techniques The IP targeted to Xilinx EPP and FPGA.
Synthesis Software Tools Supported/Version Xilinx XST / 13.2
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Lite, AXI4
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? No
Test Methodology Directed Testing
Assertions Y
Coverage Metrics Collected None
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor ModelSIM / 6.4c

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used VCK190, ZC706, ZedBoard
Industry Standard Compliance Testing Passed N
Are Test Results Available? N