logiSDHC SD Card Host Controller

  • Part Number: logiSDHC
  • Vendor: Xylon d.o.o.
  • Premier Alliance Member

Product Description

The logiSDHC Secure Digital (SD) Card Host Controller IP core is designed to transfer data from the system memory to the SD card's data bus, and vice versa. Implemented DMA mechanism enables a fast data transfer requiring minimal CPU activities. The logiSDHC IP core is SD Host Controller Standard Specification Version 2.00 compliant. The IP supports non-DMA, standard DMA and Xylon's proprietary DMA transfers, and enables expansion of embedded systems based on the Xilinx FPGA devices by mass storage capabilities. To enable easier and faster integration of the logiSDHC in FPGA designs, Xylon now ships the IP core with the FatFs file system. The FatFs is a generic file system module that implements the FAT file system on small embedded systems. The original source code can be obtained from elm-chan's web site. The logiSDHC IP core is Linux OS compatible.

Key Features and Benefits

  • 6. Supports non-DMA, standard DMA and Xylon custom DMA data transfers
  • 5. Programmabe transfer rates up to the maximum date rate specified by the standard
  • 2. Supports Standard and High Capacity SD cards
  • 1. Host Controller compliant with Secure Digital Specifications Version 2.00
  • 3. Linux OS compatible
  • 4. Delivered with the file system

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU9EG -1 Vivado 2018.3 Y 0 1317 2 0 0 0 100
KINTEX-7 Family XC7K325T -1 Vivado 2018.3 Y 567 1329 2 1 0 0 100
Zynq-7000 Family XC7Z020 -1 Vivado 2018.3 Y 584 1329 2 1 0 0 100
Spartan 6T Family XC6SLX75T -3 ISE 14.4 Y 730 1608 2 1 0 0 170
VIRTEX6LXT Family XC6VLX240T -3 ISE 14.1 Y 701 1581 2 1 0 0 320

IP Quality Metrics

General Information

This Data was Current On Nov 12, 2020
Current IP Revision Number 2.2
Date Current Revision was Released Oct 02, 2014
Release Date of First Version Mar 06, 2009

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 31
Can References be Made Available? N


IP Formats Available for Purchase Netlist, Source Code, Bitstream
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq-7000
Software Drivers Provided? Y
Driver OS Support standalone


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Instantiation, Inference
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? N
AXI Interfaces AXI4-Lite, AXI4
IP-XACT Metadata Included? Y


Is a Document Verification Plan Available? No
Test Methodology Both
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available N
Simulators Supported Mentor ModelSIM

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ZC702
Industry Standard Compliance Testing Passed N
Are Test Results Available? N