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logiI2S Audio I2S Transmitter/Receiver

  • Part Number: logiI2S
  • Vendor: Xylon d.o.o.
  • Program Tier: Premier

Product Description

The logiI2S is Xylon logicBRICKS IP core compatible with the I2S electrical serial bus interface standard used for connecting digital audio devices. This IP core enables an easy interconnection of external audio devices to the Xilinx Zynq-7000 All Programmable SoC and FPGAs that can generate or transform the digital audio data. The logiI2S IP core is fully embedded into Xilinx Vivado and ISE Design Suites, and can be easily customized and tuned for optimal slice consumption and features set. This IP core allows for an easy audio integration into Xilinx FPGA based embedded systems. Xylon provides a free reference design (logiREF-ZHMI-FMC), which includes this IP core, for the Xilinx Zynq-7000 ZC702 Evaluation Board + FMC-HMI board. This design exercises audio subsystem on Xilinx ZC702 development board and demonstrates the logiI2S functionality.


Key Features and Benefits

  • Configurable TX and RX FIFO depths
  • Configurations: receiver/transmitter, clock master/slave, word select master/slave
  • Conformant to the ARM AMBA AXI4-Lite bus
  • Supports three justification modes: normal, left and right
  • Supports up to 8x I2S instances, configurable in different ways

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K325T -2 Vivado 2016.3 Y 155 338 2 0 0 0 200
ARTIX-7 Family XC7A200T -3 Vivado 2014.3 Y 202 525 2 0 0 0 200
Zynq-7000 Family XC7Z010 -2 Vivado 2016.3 Y 139 344 2 0 0 0 200
Spartan 6 Family XC6SLX75 -3 Vivado 2013.4 Y 301 540 2 0 0 0 220
SPARTAN3E Family XC3S1200E -4 Older Version Y 78 356 0 0 0 0 220
VIRTEX6LXT Family XC6VLX75T -1 Vivado 2013.4 Y 285 565 2 0 0 0 220

IP Quality Metrics

General Information

This Data was Current On Sep 25, 2017
Current IP Revision Number 2.3.1
Date Current Revision was Released Dec 06, 2012
Release Date of First Version Jan 03, 2008

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 16
Can References be Made Available? N

Deliverables

IP Formats Available for Purchase Bitstream, Netlist, Source Code
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Spartan-6
Software Drivers Provided? Y
Driver OS Support Linux ALSA

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? Y
AXI Interfaces AXI4
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? No
Test Methodology Directed Testing
Assertions Y
Coverage Metrics Collected Assertion
Timing Verification Performed? Y
Timing Verification Report Available N
Simulators Supported Mentor ModelSIM

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ZedBoard, ZC702
Industry Standard Compliance Testing Passed N
Are Test Results Available? N
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