Bit Block Transfer 2D Graphics Accelerator

Product Description

This 2D graphics accelerator speeds up the most common GUI operations and off-loads the processor. The logiBITBLT transfers graphics objects from one part to another part of the system's on-screen or off-screen video memory, and performs different operations during transfers, such as ROP2 raster operations, bitmap scaling (stretching), Poerter & Duff compositing rules or transparency. The logiBITBLT is fully embedded into Xilinx Vivado and ISE Design Suites and its integration with on-chip AMBA AXI-4 bus is very simple. Parametrizable VHDL design allows tuning of slice consumption and features set through an easy-to-use GUI interface. The logiBITBLT can be smoothly integrated with other logicBRICKS, Xilinx or third-party IP cores for building of high-class embedded graphics solutions. Extensive software support for Linux and Microsoft Windows Embedded Compact operating systems, as well for no-OS operation, enables quick and efficient development through industry standard design flows. Free and pre-verified Xylon logicBRICKS reference designs for the most popular Zynq-7000 SoC based development kits enable developers to jump-start next designs and perform risk-free logicBRICKS evaluation.

Key Features and Benefits

  • Integrated optional up/down bitmap scaling and flipping
  • Supported image formats: RGB8, ARGB8, RGB16, ARGB16, RGB24 and ARGB24
  • Color-keyed transparency, pixel alpha blending, anti-aliased 8-bit font expansion
  • Available free reference design for development kits from Xilinx and Avnet Electronics Marketing
  • Software drivers for Linux and Microsoft WEC OS
  • Supports move operations in positive and negative directions
  • Supports 16 different ROP2 raster operations
  • Configurable Big/Little Endianess and continuous/array image addressing modes

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU9EG -1 Vivado 2017.4 Y 0 14552 14 72 0 0 214
KINTEX-7 Family XC7K325T -3 Vivado 2014.4 Y 2543 6844 14 30 0 0 150
Zynq-7000 Family XC7Z045 -2 Vivado 2017.4 Y 0 14492 14 72 0 0 160
ARTIX-7 Family XC7A35T -2 Vivado 2014.4 N 2385 6747 25 30 0 0 100

IP Quality Metrics

General Information

This Data was Current On Oct 18, 2018
Current IP Revision Number 5.5
Date Current Revision was Released Oct 15, 2018
Release Date of First Version Mar 20, 2009

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 34
Can References be Made Available? Y


IP Formats Available for Purchase Bitstream, Netlist, Source Code
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Spartan-6
Software Drivers Provided? Y
Driver OS Support Linux, WEC7


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference, Instantiation
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? Y
AXI Interfaces AXI4, AXI4-Lite
IP-XACT Metadata Included? N


Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Constrained random testing
Assertions Y
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available N
Simulators Supported Mentor ModelSIM

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used logiTAP
Industry Standard Compliance Testing Passed N
Are Test Results Available? N