Product Description
This core implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone operation, the core is ideal for offloading the host processor from the demanding task of UDP/IP encapsulation and enables media streaming with speeds up to 1Gbps even in processor-less SoC designs.
Trouble-free network operation is ensured through run-time programmability of all the required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address). The core implements the Address Resolution Protocol (ARP), which is critical for multiple access networks, and the Echo Request and Reply Messages (“ping”) of the Internet Control Message Protocol (ICMP) widely used to test network connectivity. Furthermore, the core supports 801.1Q tagging, and is suitable for operation in a Virtual LAN.
The core is easy to integrate in systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming-capable interfaces, or optionally via registers mapped on an SoC bus. The AMBA® AXI4-stream is supported. The core is Ethernet MAC-independent, but is available pre-integrated with a CAST, AMD, or other third-party eMAC core.
Key Features and Benefits
- 1 to 32 UDP transmit and 1 to UDP 32 receive channels
- Run time programmable network parameters: Local, Destination and Gateway IP address, Source and Destination UDP ports, MAC address
- Protocols, IPv4 without packet fragmentation, Jumbo and Super Jumbo Frames, ARP with Cache, ICMP (Ping), IGMP v3 (Multicast), UDP/IP Unicast and Multicast, DHCP, VLAN (802.1Q)
- 32-bit data-path and AXI-Stream data interfaces
- 10/100/1000 Mbps Ethernet with a 31.25 MHz clock
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