UDPIP - Hardware UDP/IP Stack Core

  • Part Number: UDPIP-1G
  • Vendor: CAST, Inc.
  • Partner Tier: Elite Certified

Product Description

This core implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone operation, the core is ideal for offloading the host processor from the demanding task of UDP/IP encapsulation and enables media streaming with speeds up to 1Gbps even in processor-less SoC designs.

Trouble-free network operation is ensured through run-time programmability of all the required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address). The core implements the Address Resolution Protocol (ARP), which is critical for multiple access networks, and the Echo Request and Reply Messages (“ping”) of the Internet Control Message Protocol (ICMP) widely used to test network connectivity. Furthermore, the core supports 801.1Q tagging, and is suitable for operation in a Virtual LAN.

The core is easy to integrate in systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming-capable interfaces, or optionally via registers mapped on an SoC bus. The AMBA® AXI4-stream is supported. The core is Ethernet MAC-independent, but is available pre-integrated with a CAST, AMD, or other third-party eMAC core.


Key Features and Benefits

  • 1 to 32 UDP transmit and 1 to UDP 32 receive channels
  • Run time programmable network parameters: Local, Destination and Gateway IP address, Source and Destination UDP ports, MAC address
  • Protocols, IPv4 without packet fragmentation, Jumbo and Super Jumbo Frames, ARP with Cache, ICMP (Ping), IGMP v3 (Multicast), UDP/IP Unicast and Multicast, DHCP, VLAN (802.1Q)
  • 32-bit data-path and AXI-Stream data interfaces
  • 10/100/1000 Mbps Ethernet with a 31.25 MHz clock

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Kintex-UP Family XCKU9P -1 Vivado 2019.1 Y 0 2841 2 0 0 0 125
Spartan-7 Family XC7S50 -1 Vivado 2017.4 1327 3645 3 0 0 0 125
KINTEX-7 Family XC7K325T -1 Vivado 2019.1 Y 1029 3039 3 0 0 0 125
ARTIX-7 Family XC7A100T -1 Vivado 2017.4 Y 1315 3652 3 0 0 0 125
KINTEX-U Family XCKU060 -1 Vivado 2019.1 Y 0 2841 2 0 0 0 125

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number 3v03ns00
Date Current Revision was Released Nov 18, 2019
Release Date of First Version Dec 28, 2011

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 33
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Source Code, Netlist
Source Code Format(s) Verilog
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog
Code Coverage Report Provided? Y
Functional Coverage Report Provided? Y
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Artix-7
Software Drivers Provided? N

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis; Synplicity Synplify; Mentor Precision
Static Timing Analysis Performed? Y
AXI Interfaces AXI4, AXI4-Stream, AXI4-Lite
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions N
Coverage Metrics Collected Code
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor Questa; Synopsys VCS; Mentor ModelSIM; Cadence NC-Sim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Virtex 5, Kintex-7
Industry Standard Compliance Testing Passed N
Are Test Results Available? N