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PreciseTimeBasic IEEE 1588 V2

  • Part Number: PreciseTimeBasic
  • Vendor: Soc-e
  • Program Tier: Certified

Product Description

PreciseTimeBasic is a IEEE1588-2008 V2 compliant clock synchronization IP core for Xilinx FPGAs. It is capable of accurately time stamp IEEE 1588 telegrams and also to provide a compatible time. PreciseTimeBasic IP comprises different hardware and software elements - A hardware Time Stamping Unit (TSU) capable of accurately time stamp IEEE 1588 event messages and to provide an adjustable timer with submicrosecond precision. Two versions of TSU are provided with the PreciseTimeBasic: PTB TSU and PTBLite TSU.

PTB TSU has been designed to be connected to the Medium Independent Interface ([G]MII), between MAC and PHY, parsing all the Ethernet frames and inspecting which ones are IEEE 1588. PTBLite TSU takes advantage of the PTP parser contained in the Zynq GMACs to provide a TSU usingless FPGA resources but with some limitations imposed by the IEEE 1588 hardwired logic on the PS GMAC.

With the IP, a software PTP Reference Design is also included. Additionaly, SoC-e provides a Linux kernel patch that allow accessing the TSUs using the Linux PTP Hardware Clock (PHC) subsystem.


Key Features and Benefits

  • 100/1000 Mbps ethernet
  • Available for Vivado and XPS
  • Compatible with different PTP SW stacks
  • E2E and P2P delay mechanism
  • IEEE 1588-2008 clock synchronization system
  • IRIG-B Master output
  • OC and CB working modes
  • PPS output
  • Support VLAN tagged PTP messages
  • Supports PTP on Layer 2 (Ethernet) and Layer 3 (IPv4)

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-7000 Family XC7Z020 -1 Vivado 2014.4 Y 397 672 6 0 0 0 125

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2017
Current IP Revision Number 17.08
Date Current Revision was Released Sep 01, 2017
Release Date of First Version Dec 12, 2011

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 15
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Bitstream, Netlist, Source Code
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? XDC
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq-7000
Software Drivers Provided? Y
Driver OS Support Linux

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? Y
AXI Interfaces AXI4
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? No
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available N
Simulators Supported Xilinx lSim / 2015.4

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used SMARTzynq
Industry Standard Compliance Testing Passed Y
Specific Compliance Test ISPCS2011,12,13,14,15
Test Date Dec 10, 2015
Are Test Results Available? N
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