logiI2C Serial Bus Controller

Product Description

The logiI2C is Xylon logicBRICKS IP core compatible with the I2C serial bus interface standard.It supports single master I2C communications and enables bug-free data transfers. The logiI2C supports 3 transmission speeds: • normal - 100 kbps • fast - 400 kbps • high speed - 3.5 Mbps Xylon delivers the logiI2C Master I2C Controller IP core in format fully compatible with Xilinx Vivado (IPI) and ISE (XPS) Design Suits. Provided software driver can be used with the Xilinx Software Development Kit (SDK).

Key Features and Benefits

  • ARM AMBA AXI4-Lite bus compliant
  • Software programmable I2C clock
  • Software programmable acknowledge bit for read operation
  • Start/Repeat Start/Acknowledge/Stop generation
  • Single master operation
  • Supports clock stretching/wait state generation
  • 16 location deep TX and RX FIFO
  • Available in Vivado (IPI) and ISE (XPS) formats

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU9EG -1 Vivado 2017.4 Y 0 269 0 0 0 0 325
VERSAL_AI_CORE Family XCVC1902 -1 Vivado 2019.1 0 275 0 0 0 0 400
KINTEX-7 Family XC7K325T -2 Vivado 2014.3 Y 113 318 0 0 0 0 400
Zynq-7000 Family XC7Z010 -2 Vivado 2014.3 Y 119 319 0 0 0 0 325
ARTIX-7 Family XC7A35T -2 Vivado 2017.4 Y 0 317 0 0 0 0 180

IP Quality Metrics

General Information

This Data was Current On Mar 16, 2020
Current IP Revision Number 2.1
Date Current Revision was Released Feb 06, 2020
Release Date of First Version Mar 26, 2012

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 25
Can References be Made Available? N


IP Formats Available for Purchase Source Code
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? N
Commercial Evaluation Board Available? Y
FPGA Used on Board Spartan-6
Software Drivers Provided? Y
Driver OS Support bare-metal


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Instantiation
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? N
AXI Interfaces AXI4-Lite
IP-XACT Metadata Included? N


Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Directed Testing
Assertions Y
Coverage Metrics Collected Assertion
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Mentor ModelSIM

Hardware Validation

Validated on FPGA N
Industry Standard Compliance Testing Passed N
Are Test Results Available? N