Product Description
The logiLMD Lane Marking Detection IP core from Xylon's logicBRICKS IP core library is designed to detect the lane markings on the roadway video scenarios captured from a rear-view camera, and to raise an alert in case the host's vehicle departs from the lane. Its functions include image-processing filters, like Gaussian smoothing and Edge detection, and blocks specifically tailored for lane marking detections. The output of the core is the set of straight lines corresponding to lane markings.
Key Features and Benefits
- 1. Fundamental building block for FPGA based automotive Rear Looking Lane Departure Warning System
- 2. Adopts to shadows and light changes
- 3. Hough Transform based model fitting
- 4. High input data rate; > 200 Mpix/sec
- 5. Provides high level decision making reasoning as open source embedded software
- 6. The most demanding computing tasks implemented in programmable logic
- 7. Vivado reference design (logiADAK Kit deliverable)
- 8. C code post-processing library available
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-UP-MPSoC Family | XCZU9EG | -2 | Vivado 2018.2 | 1409 | 2875 | 13 | 14 | 0 | 0 | 100 | |
| Zynq-7000 Family | XC7Z020 | -2 | Vivado 2018.2 | Y | 1409 | 2893 | 13 | 15 | 0 | 0 | 100 |
IP Quality Metrics
General Information
| This Data was Current On | Jun 12, 2019 |
| Current IP Revision Number | 2.1.2 |
| Date Current Revision was Released | Apr 10, 2019 |
| Release Date of First Version | May 17, 2012 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 5 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Netlist |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | VHDL |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | N |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Zynq-7000 |
| Software Drivers Provided? | Y |
| Driver OS Support | Linux, no OS |
Implementation
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Inference, Instantiation |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Xilinx XST |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4 |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Constrained random testing |
| Assertions | Y |
| Coverage Metrics Collected | Assertion |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | N |
| Simulators Supported | Mentor ModelSIM |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | logiADAK Automotive Driver Assistance Kit |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |