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iTOE

  • Part Number: 1G Ethernet TCP Offloading Engine
  • License: SignOnce
  • Vendor: OKI IDS Co.,Ltd.
  • Program Tier: Premier

Product Description

TCP Offloading Engine (TOE) enables TCP transfer with full band-width Gigabit Ethernet. Having TCP/IP full stack implemented in FPGA, high-speed TCP transfer as well as universal LAN communication (TCP/UDP) achieved with FPGA single chip. Complex tasks of TCP/IP protocol control are all processed with FPGA, substantially offloading the burden from host processor. With major functions required for PCI Express® and Gbit Ethernet design configuration come as a platform, Giga bit Ethernet TCP/IP Solution will help expedite time-to-market.


Key Features and Benefits

  • TCP Offloading Engine + TCP Stack

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Spartan 6T Family XC6SLX45T -2 ISE 14.3 Y 2588 5513 73 0 0 0 125

IP Quality Metrics

General Information

This Data was Current On Sep 25, 2017
Date Current Revision was Released Aug 20, 2012
Release Date of First Version Oct 10, 2010

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 15
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist
Source Code Format(s) Verilog
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog
Code Coverage Report Provided? Y
Functional Coverage Report Provided? Y
UCFs Provided? UCF
Commercial Evaluation Board Available? N
Software Drivers Provided? Y
Driver OS Support iTRON

Implementation

Code Optimized for Xilinx? Y
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? Y
AXI Interfaces AXI4
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Directed Testing
Assertions Y
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor ModelSIM

Hardware Validation

Validated on FPGA N
Industry Standard Compliance Testing Passed N
Are Test Results Available? N
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