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Omnitek Scalable Video Processor

  • Part Number: OSVP Suite
  • Vendor: Omnitek
  • Ecosystem Program Tier: Premier

Product Description

A highly configurable set of IP blocks and optional features that together provide a powerful range of tools for multi-video format conversion and image enhancement for video formats up to 60Hz Ultra HD, with 120Hz Ultra HD output as a further option. For ease of implementation and to make best use of system resources, the principal IP blocks are packaged as a single OSVP core offering up to 8 video channels that you can individually configure to carry out the precise range of actions needed to deliver the transformations you require. All interfaces conform to the AXI4 protocol. Xilinx Vivado and IPI integration is also supported. The OSVP core can be easily interfaced to video connectivity IP components from Omnitek and the Xilinx VIPP suite which are bundled with this IP module. Video channels may be of different video standards. Each of these inputs can be de-interlaced and resized, then composited onto the video output. Each video output can comprise a single video input or a composite multi-view of multiple video inputs, facilitating quad-split display, etc. The OSVP block has been optimised for Xilinx FPGA technology and achieves the highest broadcast quality video processing in an extremely small footprint IP core. A series of reference designs are available called RTVE (Real Time Video Engine). These designs integrate the OSVP IP with Xilinx VIPP in a complete working FPGA design targeted for a range of hardware platforms.


Key Features and Benefits

  • Asynchronous I/O timing
  • Cadence detector
  • Chroma resampler
  • Cropper
  • Deinterlacer
  • Detail Enhancer
  • Format Converter
  • Frame Synchronizer
  • Frame rate up to 120Hz
  • Motion and Low-angle adaptive deinterlacing
  • Resizer (scaler)
  • Video Graphic Overlay support

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K325T -1 ISE 14.4 Y 7876 19127 88 66 0 0 150000000
Zynq-7000 Family XC7Z045 -1 Vivado 2013.4 Y 7582 18412 88 66 0 0 600000000

IP Quality Metrics

General Information

This Data was Current On Sep 25, 2017
Current IP Revision Number 2.0
Date Current Revision was Released Sep 12, 2014
Release Date of First Version Sep 12, 2014

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 11
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Source Code, Bitstream
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
Software Drivers Provided? Y
Driver OS Support Linux, XilKernel

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference, Instantiation, Other Optimization Techniques
Custom FPGA Optimization Techniques None,Core Generator
Synthesis Software Tools Supported/Version Xilinx XST / 14.4
Static Timing Analysis Performed? Y
AXI Interfaces AXI4, AXI4-Stream, AXI4-Lite
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Both
Assertions Y
Coverage Metrics Collected Code, Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor ModelSIM; Xilinx lSim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used KC705 and OZ745
Industry Standard Compliance Testing Passed N
Are Test Results Available? N
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