The DSI Controller Core is part of Northwest Logic’s MIPI Solution. This solution is designed to achieve maximum MIPI throughput while being easy to use.
The core implements all three layers defined by the DSI Specification: Pixel to Byte Packing, Low Level Protocol, and Lane Management and is fully compliant with the DSI specification. Separate Host (Tx) and Peripheral (Rx) versions of the core are provided.
The core provides 4 data and 1 control/status packet interfaces. The data interfaces can be optional adapter to DBI or DPI interfaces. The control/status interface can be optionally adapted to an AXI interface. The core supports command and video modes, 1 to 4 data lanes and all data types.
The core uses the byte lane clock minimizing power consumption and ensuring the core can be used in older process technologies.
The core is delivered fully integrated and verified with the user’s target MIPI PHY. Contact Northwest Logic for a complete list of supported PHYs.
The core is also provided with the MIPI Testbench which provides a MIPI Bus Functional Model.
Northwest Logic also offers a DSI Demonstration System which includes an FPGA Board, MIPI Interface Card and MIPI Display. Contact Northwest Logic for more information.
Key Features and Benefits
- Source code available
- Provided with a MIPI DSI Testbench
- Delivered fully integrated and verified with target MIPI PHY
- 1-4 data lane support
- Supports high speed (1+ Gbit/s) and low power operation
- Support for all data types
- Optional DBI & DPI data interface and AXI control/status interface adapters
- 4 data and 1 control/status packet interfaces
- Host (Tx) and Peripheral (Rx) versions
- Fully DSI Specification compliant
- High-performance, easy-to-use core