10G TOE core, Full TCP Offload
- Part Number: INT-20011
- License: SignOnce
- Vendor: Intilop Inc
- Member Partner
Product Description
10G TCP Offload Engine+MAC+Host_IF Ultra-Low Latency (SXTOE) Fully Integrated, Verified and System tested TOE, MAC & CPU interface
Key Features and Benefits
- 10G Full TCP Offload + EMAC
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VIRTEX-7X Family | XC7VX485T | -2 | Vivado 2018.2 | N | 26941 | 84430 | 171 | 0 | 1 | 2 | 156 |
IP Quality Metrics
General Information
| This Data was Current On | May 04, 2021 |
| Current IP Revision Number | 3 |
| Date Current Revision was Released | Dec 20, 2012 |
| Release Date of First Version | Dec 20, 2011 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 15 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Netlist |
| Source Code Format(s) | Verilog |
| High-Level Model Included? | Y |
| Model Formats | Other |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | Verilog |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | UCF |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Virtex-7 |
| Software Drivers Provided? | Y |
| Driver OS Support | Windows, Linux |
Implementation
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Instantiation |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Vivado Synthesis; Xilinx XST |
| Static Timing Analysis Performed? | N |
| AXI Interfaces | AXI4-Stream |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Both |
| Assertions | Y |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Mentor ModelSIM |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | VC 707 |
| Industry Standard Compliance Testing Passed | N/A |
| Specific Compliance Test | Kelly Masood |
| Test Date | May 09, 2016 |
| Are Test Results Available? | Y |