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  3. DVB-RCS Turbo Decoder

DVB-RCS Turbo Decoder

  • Part Number: CREONIC_TURBO_DVB_RCS
  • Vendor: Creonic GmbH
  • Partner Tier: Elite Certified
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Product Description

DVB-RCS (Digital Video Broadcasting - Interaction channel for satellite distribution systems) is an established ETSI standard for digital data transmission via satellites. It uses a 8-state double-binary turbo code that has an excellent error correction performance. This outstanding performance of the DVB-RCS turbo codes makes it the ideal candidate for further applications where high spectral efficiency is key for lowering costs.

Applications

  • Satellite communication (Interactive Services, Professional Services, TDMA)
  • Applications with highest demands on forward error correction
  • Applications with the need for a wide range of code rates (1/3 and above) and block lengths

    • Key Features and Benefits

    • Compliant with ETSI 301 790 V1.4.1 (2005-09) (DVB-RCS)
    • Support for all turbo code block lengths (12 to 216 bytes) and code rates (1/3 to 6/7) as defined by the standard
    • Support for QPSK and 8-PSK interfacing
    • Design-time configuration of throughput, input bit widths, and maximum block length for optimal resource utilization.
    • Low-power and low-complexity design.
    • Burst-to-burst on-the-fly configuration.
    • Configurable interleaver parameters allow for support.

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K325T -2 Vivado ML 2022.2 N 2124 5654 5 0 0 0 250

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number 2.0.2
Date Current Revision was Released May 10, 2023
Release Date of First Version Jun 14, 2013

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 1
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) VHDL
High-Level Model Included? Y
Model Formats C, C++, Matlab
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? Y
Functional Coverage Report Provided? Y
UCFs Provided? N
Commercial Evaluation Board Available? N
Software Drivers Provided? N

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Instantiation
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Stream
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions N
Coverage Metrics Collected Code, Functional
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Other / Aldec RivieraPRO

Hardware Validation

Validated on FPGA N
Industry Standard Compliance Testing Passed N
Are Test Results Available? N