Hash Crypto Engine

  • Part Number: BA413
  • Vendor: Silex Insight
  • Certified Alliance Member
  • Application Partner

Product Description

The Hash Crypto Engine is flexible and optimized hash IP core compliant with FIPS 180-3 (HASH functions), FIPS 198 (HMAC function) and OSCCA (SM3).

With a flexible wrapper supporting a wide selection of programmable hashing modes (SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SM3 and MD5) with HMAC and several options of data interface, the Hash Crypto Engine is an easy-to-use solution with predictable resources and performances on FPGA.

Overview The Hash Crypto Engine is easily portable to FPGA. It supports a wide range of applications on various technologies. The unique architecture enables a high level of flexibility. The throughput and features required by a specific application can be taken into account in order to select the most optimal and compact configuration. Ideal for the following applications:

  • Digital signature
  • Key derivation


Key Features and Benefits

  • Supports SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SM3 and MD5
  • Supports HMAC
  • Message padding in software or hardware
  • Low power feature
  • Data interface: AMBA (AHB/AXI) with optional DMA
  • Control interface: APB/AXI4-lite

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-7000 Family XC7Z045 -3 Vivado 2018.3 Y 883 1945 0 0 0 0 275

IP Quality Metrics

General Information

This Data was Current On Dec 10, 2019
Current IP Revision Number 4
Date Current Revision was Released Mar 02, 2015
Release Date of First Version Nov 01, 2012

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 5
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq-7000
Software Drivers Provided? Y
Driver OS Support Linux Kernel Crypto API

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Instantiation
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST; Synplicity Synplify
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Lite, AXI4-Stream
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? No
Test Methodology Constrained random testing
Assertions N
Coverage Metrics Collected None
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor ModelSIM

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Zynq Development Kit
Industry Standard Compliance Testing Passed N
Are Test Results Available? N