DYPLO Dynamic Process Loader Core
Dyplo is a middleware solution to enable seamless integration of FPGA and software processes in applications. Dyplo links processes, executed on processor(s) and FPGA(s), with scalable software and hardware data streams embedded in the applied operating system. Dyplo managed processes, executed on FPGA fabric, share the same characteristics as software executed processes due to the extensive usage and support for partial reconfiguration, an advanced technology available in FPGAs. Using these properties, a full software-driven hardware development approach is made possible. This implies that the implementation of an application can be developed entirely in software while maintaining the software architecture, functions to be executed on FPGA fabric can be identified, isolated and replaced by FPGA functionality without compromising the program structure. This reduces to a high extend the low-level integration effort between FPGA and processor, which require development of bus interfaces, low level drivers and OS integration. With the partial reconfiguration FPGA fabric is reused in time, reducing the required FPGA size and as such reducing power requirements and FPGA cost.
Key Features & Benefits
- Design abstraction to system level.
- Dyplo Wizard confi guration tool to guarantee ease of use.
- High level of reuse capabilities over designs.
- Integrated support for high-level synthesis.
- Simple use of partial reconfi guration blocks in hardware.
- Software driven hardware development approach.
- Utilization of SOC devices to their maximum.
- Part Number: DYPLO
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
|Family||Device||Speed Grade||Tool Version||HW Validated?||Slice||LUT||BRAM||DSP48||CMT||GTx||FMAX (Mhz)|
|Zynq-7000 Family||XC7Z020||-1||Vivado 2015.4||Y||1503||3611||18||0||0||0||100|
IP Quality Metrics
|This Data was Current On||Aug 16, 2017|
|Current IP Revision Number||2015.4|
|Date Current Revision was Released||Feb 24, 2014|
|Release Date of First Version||Apr 18, 2014|
Production Use by Xilinx Customers
|Number of Successful Xilinx Customer Production Projects||1|
|Can References be Made Available?||Y|
|IP Formats Available for Purchase||Source Code|
|Source Code Format(s)||VHDL|
|High-Level Model Included?||N|
|Integration Testbench Provided||Y|
|Integration Test Bench Format(s)||VHDL, C/C++|
|Code Coverage Report Provided?||N|
|Functional Coverage Report Provided?||N|
|Commercial Evaluation Board Available?||Y|
|Software Drivers Provided?||Y|
|Driver OS Support||Linux|
|Code Optimized for Xilinx?||N|
|Custom FPGA Optimization Techniques||None|
|Synthesis Software Tools Supported/Version||Xilinx XST / 2013.4|
|Static Timing Analysis Performed?||Y|
|AXI Interfaces||AXI4-Stream, AXI4|
|IP-XACT Metadata Included?||N|
|Is a Document Verification Plan Available?||Executable and documented plan|
|Test Methodology||Directed Testing|
|Coverage Metrics Collected||None|
|Timing Verification Performed?||Y|
|Timing Verification Report Available||Y|
|Simulators Supported||Xilinx lSim / 2013.4; Mentor Questa / Latest; Mentor ModelSIM / Latest|
|Validated on FPGA||Y|
|Hardware Validation Platform Used||ZedBoard ZC702 ZC706|
|Industry Standard Compliance Testing Passed||N|
|Are Test Results Available?||N|