MPEG-2 Video Decoder IP Core, MPEG-2 Video/Audio Decoder IP Core
- Part Number: DC-MPEG2-IP
- Vendor: System on Chip Technologies Inc.
- Partner Tier: Elite
Product Description
MPEG-2 Video/Audio Decoder IP Core
Key Features and Benefits
- Compliance Standard: MPEG-2/H.262 (ISO/IEC 13818)
- Input Bit Rates: Up to 100Mbps
- Video Resolutions: Up to 1080i/p
- Frame Rate: Up to 60fps
- Output Chroma Formats: 4:2:2 or 4:2:0
- Input Format: MPEG-2 Elementary, or Transport Stream
- Video Output Format: RGB or YUV or YCrCb
- Power Consumption: 700mw (Core only)
- Latency: 0.25ms
- Multi-Channel: Supports multiple channels with one engine or multiple engines
- Conformance Standard for Audio: ISO/IEC 11172-4 Part 4, 1992, & ISO/IEC 13818-4 Part 4
- Output Format for Audio: Supports up to two channels (Stereo) Interleaved 16-bit PCM
- Output Bit Rate for Audio: 32-448 kbit/sec for MPEG1 L1, 32-384 kbit/sec for L2 and 32-320kbit/sec, for L3. MPEG2 & MPEG2.5, 8 – 160 kbit/s L1/L2/L3
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| ARTIX-7SLT Family | XC7A50SLT | -2 | Vivado 2020.2 | Y | 3919 | 11137 | 10 | 54 | 0 | 0 | 62 |
IP Quality Metrics
General Information
| This Data was Current On | Feb 08, 2024 |
| Current IP Revision Number | 2.20 |
| Date Current Revision was Released | Jan 16, 2012 |
| Release Date of First Version | Jan 15, 2010 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 50 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Netlist, Bitstream |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | Other |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | N |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Artix-7 |
| Software Drivers Provided? | N |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | MPEG-2 Video/Audio Decoder IP Core (for Xilinx FPGAs: Spartan-6, Artix-7, Kintex-7, and Zynq-7). |
| Synthesis Software Tools Supported/Version | Xilinx XST |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4 |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Directed Testing |
| Assertions | Y |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Xilinx lSim |
Hardware Validation
| Validated on FPGA | N |
| Industry Standard Compliance Testing Passed | Y |
| Specific Compliance Test | MPEG-2 |
| Test Date | Jan 15, 2010 |
| Are Test Results Available? | Y |