IEEE 802.1ae MACSEC for 10 Gbit Ethernet

Part Number: MACSEC-10G-XE
License: SignOnce
Vendor: Algotronix, Ltd.
Program Tier: Member

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Overview
Product Specs

Product Description

The MACSEC core is a high performance pipelined implementation of IEEE standard 802.1ae to provide cryptographic security for Ethernet networks. The MACSEC Security Entity (SecY) provides a single secure transmit channel and multiple secure receive channels with privacy, authentication, replay detection and statistics gathering for attack detection. The core is built on Algotronix' pipelined implementation of the AES-GCM encryption algorithm which itself builds on our G3 AES core. This release of the MACSEC core supports operation at 1Gbit/sec with a clock frequency of 125MHz and 10Gbit/sec with a clock frequency of 156.25MHz.

Key Features and Benefits

Complies with IEEE 802.1ae
1Gbit or 10Gbit throughput
128 or 256 bit encryption keys

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family	Device	Speed Grade	Tool Version	HW Validated?	Slice	LUT	BRAM	DSP48	CMT	GT_x	FMAX (Mhz)
VIRTEX-7X Family	XC7VX485T	-2	Vivado 2013.4	N	6638	20916	53	0	0	0	156

IP Quality Metrics

General Information

This Data was Current On	Sep 17, 2018
Current IP Revision Number	2013-1
Date Current Revision was Released	Apr 01, 2013
Release Date of First Version	Jun 23, 2010

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects	1
Can References be Made Available?	N

Deliverables

IP Formats Available for Purchase	Source Code
Source Code Format(s)	VHDL
High-Level Model Included?	Y
Model Formats	Other
Integration Testbench Provided	Y
Integration Test Bench Format(s)	VHDL
Code Coverage Report Provided?	N
Functional Coverage Report Provided?	N
UCFs Provided?	N
Commercial Evaluation Board Available?	N
Software Drivers Provided?	N

Implementation

Code Optimized for Xilinx?	Y
Standard FPGA Optimization Techniques	Instantiation, Inference
Custom FPGA Optimization Techniques	None
Synthesis Software Tools Supported/Version	Xilinx XST / 14.4
Static Timing Analysis Performed?	N
IP-XACT Metadata Included?	N

Verification

Is a Document Verification Plan Available?	Yes, document only plan
Test Methodology	Constrained random testing
Assertions	Y
Coverage Metrics Collected	None
Timing Verification Performed?	Y
Timing Verification Report Available	Y
Simulators Supported	Mentor ModelSIM / 10.1e

Hardware Validation

Validated on FPGA	N
Industry Standard Compliance Testing Passed	N
Are Test Results Available?	N

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