IPSEC Encapsulating Security Payload (RFC4303) for 1 Gbit Links

Product Description

The IPSEC core is a high performance pipelined implementation of the Encapsulating Security Protocol mode of IPSEC: those components of the standard which need to operate at line rates are implemented in hardware. (Elements such as key exchange which occur relatively infrequently are better implemented in software.) The core is built on Algotronix' pipelined implementation of the AES-GCM encryption algorithm which itself builds on our G3 AES core. This release of the IPSEC core supports operation at 1Gbit/sec and a future release will operate at 10Gbit/sec. The core is intended to eventually scale up to data rates of 100GBit/sec on Xilinx FPGAs.

Key Features and Benefits

  • Implements RFC 4303 (IP Encapsulating Security Protocol (ESP)) and RFC4106 (IPSEC with AES-GCM)
  • Supplied with comprehensive test bench containing a behavioral model of IPSEC

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-7000 Family XC7Z100 -1 Vivado 2013.4 N 4759 14158 37 0 0 0 125

IP Quality Metrics

General Information

This Data was Current On Nov 13, 2020
Current IP Revision Number 2014-1
Date Current Revision was Released May 23, 2014
Release Date of First Version May 23, 2014

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 1
Can References be Made Available? N


IP Formats Available for Purchase Source Code
Source Code Format(s) VHDL
High-Level Model Included? Y
Model Formats Other
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? N
Commercial Evaluation Board Available? N
Software Drivers Provided? N


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Instantiation, Inference
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST / 13
Static Timing Analysis Performed? Y
IP-XACT Metadata Included? N


Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions Y
Coverage Metrics Collected None
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Mentor ModelSIM / 10.1

Hardware Validation

Validated on FPGA N
Industry Standard Compliance Testing Passed N
Are Test Results Available? N