Image Signal Processing (ISP) UltraHD Pipeline

Product Description

The logiISP-UHD Image Signal Processing Pipeline IP core is an Ultra High Definition (UHD, including 4K2K) ISP pipeline designed for digital processing and image quality enhancements of an input video stream in embedded designs based on AMD MPSoC, SoC and FPGA devices. The logiISP-UHD IP core accepts diversely formatted video inputs generated by different sensors and removes defective pixels, de-mosaics Bayer encoded video, makes image color and gamma corrections, filters the noise from the video, collects video analytics data for various control algorithms and manipulates video data formats and color domains. In addition to the standard IP core deliverables, Xylon offers licensable Auto White Balancing (AWB) and Auto Exposure (AE) processor-based control algorithms that work with the video analytics data collected by the ISP pipeline.

The logiISP IP core can be easily combined with the logiHDR High Dynamic Range (HDR) Pipeline IP core into advanced video processing pipeline capable to extract the maximum detail from high contrast scenes, i.e. scenes with objects highlighted by a direct sunlight and objects placed in extreme shades.

Key Features and Benefits

  • Complete and configurable Ultra High Definition ISP pipeline
  • Digitally processes and enhances the quality of an input video stream and collects video statistics data
  • Evaluation IP core and the bit-accurate C model available on request
  • IP deliverables include the software driver, documentation and technical support
  • Configurable ISP blocks: Defective Pixel Correction, Color Filter Array Interpolation, Image Statistics, Image Enhancement, Color-Space Converters and others
  • Supports resolutions up to 7680x7680, including 4K2Kp60 (3840x2160)
  • Input video formats: Raw Bayer, RGB and YCrCb; 8/10/12-bit per pixel
  • Parallel pixel processing of 1, 2 or 4 pixels per clock
  • Video input and output are ARM AMBA AXI4-Stream protocol compliant
  • Fee-based license extension for the AWB&AE

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU9EG -2 Vivado 2020.1 Y 0 11996 30 48 0 0 320
VERSAL_AI_CORE Family XCVC1902 -2 Vivado 2020.1 Y 0 12767 30 48 0 0 250
Zynq-7000 Family XC7Z045 -2 Vivado 2020.1 Y 0 12100 30 51 0 0 150

IP Quality Metrics

General Information

This Data was Current On Jun 24, 2023
Current IP Revision Number 3.0
Date Current Revision was Released Mar 10, 2021
Release Date of First Version Dec 09, 2014

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 15
Can References be Made Available? N


IP Formats Available for Purchase Netlist
Source Code Format(s) VHDL
High-Level Model Included? Y
Model Formats C
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? N
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq UltraScale+ MPSoC
Software Drivers Provided? Y
Driver OS Support no OS


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference, Instantiation, UltraFast Design Methodology
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? N
AXI Interfaces AXI4-Stream, AXI4-Lite
IP-XACT Metadata Included? Y


Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Both
Assertions Y
Coverage Metrics Collected Assertion
Timing Verification Performed? Y
Timing Verification Report Available N
Simulators Supported Mentor ModelSIM

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used logiISP-ZU-GMSL2 HDR ISP Evaluation Kit
Industry Standard Compliance Testing Passed N
Are Test Results Available? N