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DVB-C Modulator J83 Annex A/C

  • Part Number: MVD_DVBC_J83AC
  • License: SignOnce
  • Vendor: Multi Video Designs
  • Ecosystem Program Tier: Member

Product Description

The DVB-C J.83A/C cable modulator modulates an MPEG-TS DVB-SPI input into a QAM-16/32/65/128/256 output in base band or Intermediate Frequency (IF), according to ITU-T J.83 Annex A/C / DVB-C (ETS 300 429) standards.

Key Features and Benefits

  • Netlist version available for ISE and VIVADO
  • Full synthesizable RTL VHDL design (not delivered) for easy customization
  • MER > 42dB
  • Single / multi channel
  • Intermediate frequency output for single DAC (14 bits) or baseband outputs (2 x 16 bits)
  • Programmable 16, 32, 64, 128 and 256 QAM Symbol Mapping
  • Supports programmable symbol rates
  • PCR re-stamping
  • Robust SPI input (discarding incorrect input packets)

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K325T -2 Vivado 2017.4 N 1494 4021 2 22 1 0 150

IP Quality Metrics

General Information

This Data was Current On Dec 10, 2018
Current IP Revision Number 5.0
Date Current Revision was Released Nov 02, 2015
Release Date of First Version Sep 01, 2007

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 17
Can References be Made Available? Y


IP Formats Available for Purchase Bitstream, Netlist, Source Code
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Spartan-6
Software Drivers Provided? N/A


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Instantiation
Synthesis Software Tools Supported/Version Xilinx XST; Vivado Synthesis
Static Timing Analysis Performed? Y
IP-XACT Metadata Included? N


Is a Document Verification Plan Available? No
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Xilinx lSim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used SP605/ML605/KC705 + MVD evaluation board
Industry Standard Compliance Testing Passed N
Are Test Results Available? N
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