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BA110 JPEG 2000 multi-channel HD/DCI encoder

  • Part Number: BA110
  • Vendor: Silex Insight
  • Certified Alliance Member
  • Accelerator Program Partner

Product Description

The BA110 IP core is a JPEG 2000 hardware encoder dedicated to DCI (Digital Cinema Initiatives) and HD video applications. It performs the JPEG 2000 encoding on un-tiled large color frames with 4:4:4 or 4:2:2 sub-sampling. It generates streams compliant with the ISO/IEC 15444-1 specification (JPEG 2000).

The core performs the following video compression operations of the normalized encoding process: color transform (ICT/RCT), discrete wavelet transform (DWT), quantization, entropy encoding and rate allocation. It accepts pixels on its input interface with up to 12 bits per color components (up to 16 bits in lossless mode). It generates a j2c JPEG 2000 stream at its output interface.

The core is optimized for speed and is able to deal with the demanding DCI and HD processing requirements: it is able to provide a single-chip FPGA solution for all 2K@24 fps, 2K@48fps, 2K3D@24fps, 4K@24fps, 4K3D@24fps, 720p30/60, 1080i and 1080p30/60 distributions.

The flexible FPGA architecture allows the user to build a secure encoder by integrating Barco Silex cryptography encoders.

Key Features and Benefits

  • Compliant with JPEG 2000 (ISO/IEC 15444-1) and DCI (Digital Cinema Initiatives) recommendation.
  • Configurable encoded bit rate with 3 selectable regulation modes up to 250Mbps / 500Mbps / 1+Gbps / lossless.
  • Flexible IP core with support for a wide range of JPEG 2000 options and easy to use interface for simple integration.
  • Full-frame encoding (no tiling).
  • XYZ, RGB, YUV (4:4:4 or 4:2:2) color spaces with support for ICT/RCT color transform.
  • Multi-channel interface.
  • Pixel depth up to 12 bits per color sample (lossless mode up to 16 bits).
  • Single-chip FPGA solution for single-channel or multi-channel up to 4096x2160 (4K) resolution.
  • Fully synchronous design.

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
ARTIX-7 Family XC7A200T -1 ISE 14.4 Y 0 0 0 0 0 0 0

IP Quality Metrics

General Information

This Data was Current On Aug 23, 2018
Current IP Revision Number 2.0
Date Current Revision was Released Sep 11, 2012
Release Date of First Version Jul 13, 2007

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 10
Can References be Made Available? N


IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Virtex-5
Software Drivers Provided? Y
Driver OS Support Windows XP, Windows Vista, Linux


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference, Instantiation
Custom FPGA Optimization Techniques Memories & DSP
Synthesis Software Tools Supported/Version Synplicity Synplify / All; Xilinx XST / All
Static Timing Analysis Performed? Y
IP-XACT Metadata Included? N


Is a Document Verification Plan Available? Yes, executable and documented
Test Methodology Directed Testing
Assertions Y
Coverage Metrics Collected None
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Mentor ModelSIM / All; Other / All

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Virtex-5, Virtex-6, Kintex-7
Industry Standard Compliance Testing Passed N/A
Specific Compliance Test N/A
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