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DVB-S Modulator

  • Part Number: MVD_DVBS
  • License: SignOnce
  • Vendor: Multi Video Designs
  • Ecosystem Program Tier: Member

Product Description

The DVB-S modulator modulates an MPEG-TS DVB-SPI input into a QPSK output in Intermediate Frequency (IF), according to ETS 300 421 standard.

Key Features and Benefits

  • Netlist version available for ISE and VIVADO
  • Full synthesizable RTL VHDL design (not delivered) for easy customization
  • MER > 40dB
  • Single / multi channel
  • Baseband or Intermediate frequency output for complex DAC (2 x 16 bits)
  • Programmable 1/2, 2/3, 3/4, 5/6 and 7/8 punctured FEC
  • Supports programmable symbol rates
  • PCR re-stamping
  • Robust SPI input (discarding incorrect input packets)
  • Single clock (up to 150 MHz)

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K325T -2 Vivado 2017.4 Y 1693 3960 4 2 1 0 150
Spartan 6T Family XC6SLX45T -3 ISE 13.4 Y 1276 4659 3 16 1 0 150

IP Quality Metrics

General Information

This Data was Current On Dec 10, 2018
Current IP Revision Number 5.0
Date Current Revision was Released Jan 04, 2016
Release Date of First Version May 01, 2008

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 0
Can References be Made Available? N


IP Formats Available for Purchase Bitstream, Netlist, Source Code
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Spartan-6
Software Drivers Provided? N/A


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Instantiation
Synthesis Software Tools Supported/Version Xilinx XST; Vivado Synthesis
Static Timing Analysis Performed? Y
IP-XACT Metadata Included? N


Is a Document Verification Plan Available? No
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Xilinx lSim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used SP605/ML605/KC705 + Analog Devices AD9739 FMC Card
Industry Standard Compliance Testing Passed N
Are Test Results Available? N
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