The Rambus DMA Back-End Core provides high-performance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems. The core works with the Xilinx FPGA hard cores. It can be configured with multiple DMA Engines which each have their own interface. It supports Packet/Block and Addressed/Non-addressed transfers. Host-based and local descriptors are supported. The core supports legacy, MSI and MSI-X interrupts. Using the core eliminates the need for the user to implement their own DMA design, significantly reducing development time and risk. Companion Windows and Linux DMA drivers are available. The DMA Back-End Driver works hand-in-hand with the DMA Back-End core to implement host-based, scatter-gather DMA operation. Note: Utilization numbers provided in the 'IP Implementation and Quality Metrics' tab is for a x1 lane DMA Back-End Core implementation
Device utilization metrics for example implementations of this core. Contact provider for more information.
Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
---|---|---|---|---|---|---|---|---|---|---|---|
KINTEX-7 Family | XC7K325T | -1 | Vivado 2018.3 | Y | 2794 | 7412 | 3 | 0 | 0 | 0 | 250 |
This Data was Current On | Oct 05, 2022 |
Current IP Revision Number | 4.24 |
Date Current Revision was Released | Jun 07, 2016 |
Release Date of First Version | Jul 07, 2007 |
Number of Successful Xilinx Customer Production Projects | 283 |
Can References be Made Available? | Y |
IP Formats Available for Purchase | Netlist, Source Code |
Source Code Format(s) | Verilog |
High-Level Model Included? | N |
Integration Testbench Provided | Y |
Integration Test Bench Format(s) | Verilog |
Code Coverage Report Provided? | Y |
Functional Coverage Report Provided? | Y |
UCFs Provided? | UCF |
Commercial Evaluation Board Available? | Y |
Software Drivers Provided? | Y |
Driver OS Support | Windows, Linux |
Code Optimized for Xilinx? | Y |
Standard FPGA Optimization Techniques | Inference |
Custom FPGA Optimization Techniques | Optimized levels of logic for FPGA operation |
Synthesis Software Tools Supported/Version | Xilinx XST / All; Synplicity Synplify / All; Mentor Precision / All |
Static Timing Analysis Performed? | Y |
IP-XACT Metadata Included? | N |
Is a Document Verification Plan Available? | Yes, document only plan |
Test Methodology | Both |
Assertions | N |
Coverage Metrics Collected | Code, Functional |
Timing Verification Performed? | Y |
Timing Verification Report Available | Y |
Simulators Supported | Mentor ModelSIM / All; Xilinx lSim / All; Cadence NC-Sim / All; Cadence IUS / All; Mentor Questa / All; Synopsys VCS / All; Other / ALdec RiveraPro/Active-HDL; Other / Synapticad Verilogger |
Validated on FPGA | Y |
Hardware Validation Platform Used | multiple platforms |
Industry Standard Compliance Testing Passed | Y |
Specific Compliance Test | PCI-SIG Compliance Workshop |
Test Date | Nov 19, 2008 |
Are Test Results Available? | Y |