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  3. PCI Express DMA Back-End Core (NWL)

PCI Express DMA Back-End Core (NWL)

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Product Description

The Rambus DMA Back-End Core provides high-performance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems. Using the core eliminates the need for the user to implement their own DMA design, significantly reducing development time and risk.

Note: Utilization numbers provided in the 'IP Implementation and Quality Metrics' tab is for a x1 lane DMA Back-End Core implementation

Key Features and Benefits

  • Utilization numbers provided in the IP Implementation and Quality Metrics are for a x1 lane PCIe implementation
  • Provided with a PCI Express Testbench
  • Works with Xilinx PCI Express hard cores and Northwest Logic soft PCI Express cores
  • Fully hardware validated
  • Supports host-based and local descriptors
  • Supports Packet/Block and Addressed/Non-addressed transfers
  • Provides maximum DMA throughput in both System->Card and Card->System directions
  • Also available with AXI user interface
  • Companion Windows and Linux DMA Drivers available
  • Can be configured with multiple independent DMA Engines
  • Provides high performance, scatter-gather DMA operation

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K325T -1 Vivado 2018.3 Y 2794 7412 3 0 0 0 250

IP Quality Metrics

General Information

This Data was Current On Jan 25, 2022
Current IP Revision Number 4.24
Date Current Revision was Released Jun 07, 2016
Release Date of First Version Jul 07, 2007

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 283
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) Verilog
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog
Code Coverage Report Provided? Y
Functional Coverage Report Provided? Y
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
Software Drivers Provided? Y
Driver OS Support Windows, Linux

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference
Custom FPGA Optimization Techniques Optimized levels of logic for FPGA operation
Synthesis Software Tools Supported/Version Xilinx XST / All; Synplicity Synplify / All; Mentor Precision / All
Static Timing Analysis Performed? Y
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions N
Coverage Metrics Collected Code, Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor ModelSIM / All; Xilinx lSim / All; Cadence NC-Sim / All; Cadence IUS / All; Mentor Questa / All; Synopsys VCS / All; Other / ALdec RiveraPro/Active-HDL; Other / Synapticad Verilogger

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used multiple platforms
Industry Standard Compliance Testing Passed Y
Specific Compliance Test PCI-SIG Compliance Workshop
Test Date Nov 19, 2008
Are Test Results Available? Y