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GigE for Machine Vision (GigEVCore1.2)

  • Part Number: GigEVCore1.2
  • License: SignOnce
  • Vendor: Sensor to Image GmbH
  • Program Tier: Certified

Product Description

The machine vision GigE solution consists of one or more FPGA IP cores to design GigE Vision compliant devices mainly for machine vision market. Devices could be cameras, but also receiving component like specialized GigE frame grabbers. The solution maps GigE Visions’s control channel and message channels to a software implemented part, running on an embedded processor like MicroBlaze. The time critical stream channel is fully implemented in hardware to achieve maximum of throughput. Customer is able to use this core to bring GigE Vision functionality to his device. Software can be customized to support device dependent features. Reference Designs (hardware plus FPGA design) for sending and receiving applications show usage of the core and help implementation on own hardware.


Key Features and Benefits

  • Bidirectional Streaming supported
  • Control Channel handled by embbeded CPU.
  • Hardware Implementation of Stream Channel to reach maximum troughput
  • Implementation of GigE Vision Protocol
  • Packet Resend supported.
  • Reference Design for sending and receving applications available.
  • Tiny sdram controller avilable or MPMC supported.

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
ARTIX-7 Family XC7A200T -3 Vivado 2013.4 Y 31648 25423 19 6 4 0 150
Zynq-7000 Family XC7Z015 -2 Vivado 2014.2 Y 7089 10950 12 1 2 0 220

IP Quality Metrics

General Information

This Data was Current On Sep 25, 2017
Current IP Revision Number 1.2
Date Current Revision was Released Oct 14, 2016
Release Date of First Version May 01, 2009

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 50
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Source Code, Netlist
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Artix-7
Software Drivers Provided? Y
Driver OS Support Windows and LINUX

Implementation

Code Optimized for Xilinx? N
Synthesis Software Tools Supported/Version Xilinx XST / 11.5, 12.1
Static Timing Analysis Performed? Y
AXI Interfaces AXI4
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Directed Testing
Assertions Y
Coverage Metrics Collected Code, Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor ModelSIM / 6.5DE

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used SP605, AC701, KC705, ZC706
Industry Standard Compliance Testing Passed Y
Specific Compliance Test http://www.visiononline.org/product-catalog-detail.cfm?productid=3328
Test Date Nov 12, 2010
Are Test Results Available? Y
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